B3.3 MPU register summary

The Memory Protection Unit (MPU) has various registers associated to its function.

Each of these registers is 32 bits wide. If the MPU is not present in the implementation, then all of these registers read as zero. The following table shows the MPU register summary.

Table B3-2 MPU register summary

Address Name Type Reset value Processor security state Description
0xE000ED90 MPU_TYPE RO 0x0000xx00a Secure MPU Type Register (S)
  0x0000xx00b Non-secure MPU Type Register (NS)
0xE002ED90 MPU_TYPE_NS   0x0000xx00b Secure MPU Type Register (NS)
    Non-secure RAZ/WI
0xE000ED94 MPU_CTRL RW 0x00000000 Secure MPU Control Register (S)
  0x00000000 Non-secure MPU Control register (NS)
0xE002ED94 MPU_CTRL_NS   0x00000000 Secure MPU Control register (NS)
    Non-secure RAZ/WI
0xE000ED98 MPU_RNR RW UNKNOWN Secure MPU Region Number Register (S)
  UNKNOWN Non-secure MPU Region Number Register (NS)
0xE002ED98 MPU_ RNR_NS RW UNKNOWN Secure MPU Region Number Register (NS)
    Non-secure RAZ/WI
0xE000ED9C MPU_RBAR_A0-MPU_RBAR_A3 RW UNKNOWN Secure MPU Region Base Address Register Aliases 0-3 (S)
  UNKNOWN Non-secure MPU Region Base Address Register Aliases 0-3 (NS)
0xE002ED9C MPU_RBAR_A_0_NS-MPU_RBAR_A_3_NS RW UNKNOWN Secure MPU Region Base Address Register Aliases 0-3 (NS)
    Non-secure RAZ/WI
0xE000EDA0 MPU_RLAR_A0-MPU_RLAR_A3 RW UNKNOWN Secure MPU Region Limit Address Register Aliases 0-3 (S)
  UNKNOWN Non-secure MPU Region Limit Address Register Aliases 0-3 (NS)
0xE002EDA0 MPU_RLAR_A_0_NS- MPU_RLAR_A_3_NS RW UNKNOWN Secure MPU Region Limit Address Register Aliases 0-3 (NS)
    Non-secure RAZ/WI
0xE000EDC0 MPU_MAIR0 RW UNKNOWN Secure MPU Memory Attribute Indirection Register 0 (S)
  UNKNOWN Non-secure MPU Memory Attribute Indirection Register 0 (NS)
0xE002EDC0 MPU_MAIR0_NS RW UNKNOWN Secure MPU Memory Attribute Indirection Register 0 (NS)
    Non-secure RAZ/WI
0xE000EDC4 MPU_MAIR1 RW UNKNOWN Secure MPU Memory Attribute Indirection Register 1 (S)
  UNKNOWN Non-secure MPU Memory Attribute Indirection Register 1 (NS)
0xE002EDC4 MPU_MAIR1_NS RW UNKNOWN Secure MPU Memory Attribute Indirection Register 1 (NS)
    Non-secure RAZ/WI

See the Armv8‑M Architecture Reference Manual for more information about the MPU registers and their addresses, access types, and reset values.

a MPU_TYPE[15:8] depends on the number of Secure MPU regions configured. This value can be 0, 4, 8, 12, or 16.
b MPU_TYPE[15:8] depends on the number of Non-secure MPU regions configured. This value can be 0, 4, 8, 12, or 16.
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