B3.2 SAU register summary

Each of these registers is 32 bits wide. The following table shows the SAU register summary.

Address Name Type Reset value Processor security state Description
0xE000EDD0 SAU_CTRL RW 0x00000000 Secure SAU Control register
    Non-secure RAZ/WI
0xE000EDD4 SAU_TYPE RO 0000000xa Secure SAU Type register
    Non-secure RAZ/WI
0xE000EDD8 SAU_RNR RW UNKNOWN Secure SAU Region Number Register
    Non-secure RAZ/WI
E000EDDC SAU_RBAR RW UNKNOWN Secure SAU Region Base Address Register
    Non-secure RAZ/WI
0xE000EDE0 SAU_RLAR RW UNKNOWN Secure SAU Region Limit Address Register
    Non-secure RAZ/WI

See the Armv8‑M Architecture Reference Manual for more information about the SAU registers and their addresses, access types, and reset values.

a SAU_TYPE[7:0] depends on the number of SAU regions included. This value can be 0, 4, or 8.
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