B1.4.1 Private Peripheral Bus
The Private Peripheral Bus (PPB) memory region provides access to internal and external processor resources.
The internal PPB provides access to:
- The System Control Space (SCS), including the
Memory Protection Unit (MPU), Secure Attribution Unit (SAU), if included, and the Nested
Vectored Interrupt Controller (NVIC).
- The Data Watchpoint and Trace (DWT) unit, if included.
- The Breakpoint Unit (BPU), if included.
- The Embedded Trace Macrocell (ETM), if
- CoreSight Micro Trace Buffer (MTB), if included.
- Cross Trigger Interface (CTI), if included.
- The ROM table.
The external PPB (EPPB) provides access to:
- Implementation-specific external areas of the PPB memory map.