B2.2 Auxiliary Control Register

The ACTLR Register contains a number of fields that allow software to control the processor features and functionality.

Usage constraintsPrivileged access permitted only. Unprivileged accesses generate a fault.
ConfigurationsThis register is always implemented.
AttributesA 32-bit RW register located at 0xE000E008. Non-secure alias is provided using ACTLR_NS, located at 0xE002E008. This register is banked between Security domains.
Field Name Description
[31:30] Reserved These bits are reserved for future use and must be treated as UNK/SBZP.
[29] EXTEXCLALL

0= Normal operation; memory requests on C-AHB or S-AHB interfaces associated with LDREX and STREX instructions or LDAEX and STLEX instructions only assert HEXCL and respond to HEXOKAY if the address is shareable.

1= All memory requests on C-AHB or S-AHB interfaces associated with LDREX and STREX instructions or LDAEX and STLEX instructions assert HEXCL and respond to HEXOKAY irrespective of the shareable attribute associated with the address.

Setting EXTEXCLALL allows external exclusive operations to be used in a configuration with no MPU. This is because the default memory map does not include any shareable Normal memory.

[28:13] Reserved These bits are reserved for future use and must be treated as UNK/SBZP
[12] DISITMATBFLUSH

0= Normal operation.

1= ITM/DWT ATB flush disabled.

When disabled AFVALID is ignored and AFREADY is held HIGH.

[11] Reserved This bit is reserved for future use and must be treated as UNK/SBZP
[10] FPEXCODIS

0= normal operation

1= FPU exception outputs are disabled

See Floating-point Unit Chapter for more information about the FPU exception outputs.

[9] DISOOFP

0= normal operation

1= disables floating-point instructions completing out of order with respect to non-floating-point instructions.

[8:3] Reserved These bits are reserved for future use and must be treated as UNK/SBZP.
[2] DISFOLD

0= normal operation.

1= dual-issue functionality is disabled

Note:

Setting this bit decreases performance.
[1] Reserved These bits are reserved for future use and must be treated as UNK/SBZP.
[0] DISMCYCINT

0= normal operation.

1= disables interruption of multi-cycle instructions. This increases the interrupt latency of the processor because load/store and multiply/divide operations complete before interrupt stacking occurs.

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