C5.2 BPU programmers model

The following table shows the BPU registers, with address, name, type and reset information for each register.

Depending on the implementation of your processor, some of these registers might not be present. Any register that is configured as not present reads as zero and ignores writes.

All BPU registers are described in the Armv8‑M Architecture Reference Manual.

Table C5-1 BPU register summary

Address offset Name Type Reset value Description
0xE0002000 FP_CTRL RW

0x10000040

If four instruction comparators are implemented.

0x10000080

If eight instruction comparators are implemented.

FlashPatch Control Register
0xE0002004 FP_REMAP RAZ/WI - Flash Patch Remap Register not implemented
0xE0002008 FP_COMP0a RW 0x00000000 FlashPatch Comparator Register0
0xE000200C FP_COMP1a RW 0x00000000 Flash Patch Comparator Register 1
0xE0002010 FP_COMP2a RW 0x00000000 Flash Patch Comparator Register 2
0xE0002014 FP_COMP3a RW 0x00000000 Flash Patch Comparator Register 3
0xE0002018 FP_COMP4a RW 0x00000000 Flash Patch Comparator Register 4
0xE000201C FP_COMP5a RW 0x00000000 FlashPatch Comparator Register 5
0xE0002020 FP_COMP6a RW 0x00000000 Flash Patch Comparator Register 6
0xE0002024 FP_COMP7a RW 0x00000000 Flash Patch Comparator Register 7
0xE0002FCC FP_DEVTYPE RO 0x00000000 FPB CoreSight Device Type Register
0xE0002FBC FP_DEVARCH RO 0x47701A03 FPB CoreSight Device Architecture Register
0xE0002FD0 FP_PIDR4 RO 0x00000004 Peripheral identification registers
0xE0002FD4 FP_PIDR5 RO 0x00000000
0xE0002FD8 FP_PIDR6 RO 0x00000000
0xE0002FDC FP_PIDR7 RO 0x00000000
0xE0002FE0 FP_PIDR0 RO 0x00000021
0xE0002FE4 FP_PIDR1 RO 0x000000BD
0xE0002FE8 FP_PIDR2 RO 0x0000000B
0xE0002FEC FP_PIDR3 RO 0x00000000a
0xE0002FF0 FP_CIDR0 RO 0x0000000D Component identification registers
0xE0002FF4 FP_CIDR1 RO 0x00000090
0xE0002FF8 FP_CIDR2 RO 0x00000005
0xE0002FFC FP_CIDR3 RO 0x000000B1
a 

FP_COMPn[0] is reset to 0.

FP_COMPn[31:1] is reset to unknown

If only 4 breakpoints are implemented, FP_COMP4-FP_COMP7 are RAZ/WI.

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