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When a debugger identifies the SCS from its CoreSight™ identification, it can identify the processor and its revision number from the CPUID register in the SCS at address
A debugger cannot rely on the Cortex®‑M33 Processor ROM table being the first ROM table encountered. One or more system ROM tables might be included between the access port and the processor ROM table if other CoreSight components are in the system. If a system ROM table is present, it can include a unique identifier for the implementation.