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Home > Debug and trace components > Debug > Debug functionality > Processor ROM table identification and entries |
The ROM table identification registers and values that the following table shows allow debuggers to identify the processor and its debug capabilities.
Table C1-1 Cortex®‑M33 Processor ROM table identification values
Address offset | Register | Value | Description |
---|---|---|---|
0xE00FFFD0 |
PIDR4 |
|
Component and Peripheral ID register formats in the Armv8‑M Architecture Reference Manual |
0xE00FFFD4 |
PIDR5 |
|
|
0xE00FFFD8 |
PIDR6 |
|
|
0xE00FFFDC |
PIDR7 |
|
|
0xE00FFFE0 |
PIDR0 |
|
|
0xE00FFFE4 |
PIDR1 |
|
|
0xE00FFFE8 |
PIDR2 |
|
|
0xE00FFFEC |
PIDR3 | a |
|
0xE00FFFF0 |
CIDR0 |
|
|
0xE00FFFF4 |
CIDR1 |
|
|
0xE00FFFF8 |
CIDR2 |
|
|
0xE00FFFFC |
CIDR3 |
|
These values for the Peripheral ID registers identify this as the Cortex‑M33 Processor ROM table. The Component ID registers identify this as a CoreSight™ ROM table.
The following table shows the CoreSight components that the Cortex‑M33 Processor ROM table points to.
Table C1-2 Cortex‑M33 Processor ROM table components
Address | Component | Value | Description |
---|---|---|---|
|
SCS | . |
See System Control. |
|
DWT | . Reads as
|
See DWT |
|
BPU | . Reads as
|
See BPU |
|
ITM | . Reads as
|
See ITM. |
|
ETM | . Reads as
|
See the Arm® CoreSight™ ETM-Cortex®‑M33 Technical Reference Manual |
|
CTI | . Reads as
|
See CTI. |
|
MTB | . Reads as
|
See MTB. |
-
|
Reserved | . |
See the Arm® CoreSight™ Architecture Specification (v2.0) |
|
SYSTEM ACCESS | . |
The Cortex‑M33
Processor ROM table entries point to the debug components of the processor. The offset for
each entry is the offset of that component from the ROM table base address,
.0xE00FF000
See the Arm® CoreSight™ Architecture Specification (v2.0) for more information about the ROM table ID and component registers, and access types.