Arm Cortex‑M33 Processor Technical Reference Manual : C1.1.3 Processor ROM table identification and entries

C1.1.3 Processor ROM table identification and entries

The ROM table identification registers and values that the following table shows allow debuggers to identify the processor and its debug capabilities.

Table C1-1 Cortex^®‑M33 Processor ROM table identification values

Address offset	Register	Value	Description
`0xE00FFFD0`	PIDR4	`0x00000004`	Component and Peripheral ID register formats in the Armv8‑M Architecture Reference Manual
`0xE00FFFD4`	PIDR5	`0x00000000`
`0xE00FFFD8`	PIDR6	`0x00000000`
`0xE00FFFDC`	PIDR7	`0x00000000`
`0xE00FFFE0`	PIDR0	`0x000000C9`
`0xE00FFFE4`	PIDR1	`0x000000B4`
`0xE00FFFE8`	PIDR2	`0x0000000B`
`0xE00FFFEC`	PIDR3	`0x00000000`^a
`0xE00FFFF0`	CIDR0	`0x0000000D`
`0xE00FFFF4`	CIDR1	`0x00000010`
`0xE00FFFF8`	CIDR2	`0x00000005`
`0xE00FFFFC`	CIDR3	`0x000000B1`

These values for the Peripheral ID registers identify this as the Cortex‑M33 Processor ROM table. The Component ID registers identify this as a CoreSight™ ROM table.

Note:

The Cortex‑M33 Processor ROM table only supports word-size transactions.

The following table shows the CoreSight components that the Cortex‑M33 Processor ROM table points to.

Table C1-2 Cortex‑M33 Processor ROM table components

Address	Component	Value	Description
`0xE00FF000`	SCS	`0xFFF0F003`.	See System Control.
`0xE00FF004`	DWT	`0xFFF02003`. Reads as `0xFFF02002` if the DWT is not implemented.	See DWT
`0xE00FF008`	BPU	`0xFFF03003`. Reads as `0xFFF03002` if the BPU is not implemented.	See BPU
`0xE00FF00C`	ITM	`0xFFF01003`. Reads as `0xFFF01002` if the ITM is not implemented.	See ITM.
`0xE00FF014`	ETM	`0xFFF42003`. Reads as `0xFFF42002` if the ETM is not implemented.	See the Arm^® CoreSight™ ETM-Cortex^®‑M33 Technical Reference Manual
`0xE00FF018`	CTI	`0xFFF43003`. Reads as `0xFFF43002` if the CTI is not implemented.	See CTI.
`0xE00FF01C`	MTB	`0xFFF44003`. Reads as `0xFFF44002` if the MTB is not implemented.	See MTB.
`0xE00FF020`-`0xE00FFFC8`	Reserved	`0x00000000`.	See the Arm^® CoreSight™ Architecture Specification (v2.0)
`0xE00FFFCC`	SYSTEM ACCESS	`0x00000001`.	See the Arm^® CoreSight™ Architecture Specification (v2.0)

The Cortex‑M33 Processor ROM table entries point to the debug components of the processor. The offset for each entry is the offset of that component from the ROM table base address, 0xE00FF000.

See the Arm^® CoreSight™ Architecture Specification (v2.0) for more information about the ROM table ID and component registers, and access types.

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