C1.1.5 Debug register summary

The following table shows the debug registers, with address, name, type, reset, and description information for each register.

Each register is 32-bits wide and is described in the Armv8‑M Architecture Reference Manual.

Table C1-4 Debug registers

Address offset Name Type Reset value Processor security state Description
0xE000ED30 DFSR RW 0x00000000

Power-on reset only.

Secure Debug Fault Status Register
Non-secure
0xE002ED30 DFSR_NS RW 0x00000000 Secure Debug Fault Status Register (NS)
- Non-secure RAZ/WI
0xE000EDF0 DHCSR RW 0x00000000 Secure Debug Halting Control and Status Register
Non-secure
0xE002EDF0 DHCSR_NS RW 0x00000000 Secure Debug Halting Control and Status Register (NS)
- Non-secure RAZ/WI
0xE000EDF4 DCRSR WO UNKNOWN Secure Debug Core Register Selector Register
Non-secure
0xE000EDF8 DCRDR RW UNKNOWN Secure Debug Core Register Data Register
Non-secure
0xE002EDF8 DCRDR_NS RW UNKNOWN Secure Debug Core Register Data Register (NS)
- Non-secure RAZ/WI
0xE000EDFC DEMCR RW 0x00000000 Secure Debug Exception and Monitor Control Register
Non-secure
0xE000EDFC DEMCR_NS RW 0x00000000 Secure Debug Exception and Monitor Control Register (NS)
- Non-secure RAZ/WI
0xE000EE04 DAUTHCTRL RW 0x00000000 Secure Debug Authentication Control Register
Non-secure
0xE002EE04 DAUTHCTRL_NS RW 0x00000000 Secure Debug Authentication Control Register (ns)
- Non-secure RAZ/WI
0xE000EE08 DSCSR RW 0x00000000 Secure Debug Security Control and Status Register
Non-secure
0xE000EFB8 DAUTHSTATUS RO UNKNOWNa Secure Debug Authentication Status Register
Non-secure
0xE002EFB8 DAUTHSTATUS_NS RO UNKNOWNa Secure Debug Authentication Status Register (ns)
  Non-secure RAZ/WI

a The value of DAUTHSTATUS at reset is dependent on the debug authentication defined in the system and whether the Armv8‑M Security Extension is included in the processor. Armv8‑M Architecture Reference Manual for more information.
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