C4.2 CTI functional description

The Cortex®‑M33 CTI interacts with several debug system components, and is connected to various trigger inputs and trigger outputs.

The following figure shows the debug system components and the available trigger inputs and trigger outputs.

Figure C4-1 Debug system components
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The following table shows how the CTI trigger inputs are connected to the Cortex‑M33 processor.

Table C4-1 Trigger signals to the CTI

Signal Description Connection Acknowledge, handshake
CTITRIGIN[7] - ETM to CTI Pulsed
CTITRIGIN[6] -
CTITRIGIN[5] ETM Event Output 1
CTITRIGIN[4] ETM Event Output 0 or Comparator Output 3 ETM/Processor to CTI
CTITRIGIN[3] DWT Comparator Output 2 Processor to CTI
CTITRIGIN[2] DWT Comparator Output 1
CTITRIGIN[1] DWT Comparator Output 0
CTITRIGIN[0] Processor Halted

The following table shows how the CTI trigger outputs are connected to the processor and ETM.

Table C4-2 Trigger signals from the CTI

Signal Description Connection Acknowledge, handshake
CTITRIGOUT[7] ETM Event Input 3 CTI to ETM Pulsed
CTITRIGOUT[6] ETM Event Input 2 Pulsed
CTITRIGOUT[5] ETM Event Input 1 or MTB Trace stop CTI to ETM or MTB Pulsed
CTITRIGOUT[4] ETM Event Input 0 or MTB Trace start Pulsed
CTITRIGOUT[3] Interrupt request 1 CTI to system. Acknowledged by writing to the CTIINTACK register in ISR
CTITRIGOUT[2] Interrupt request 0
CTITRIGOUT[1] Processor Restart CTI to Processor Processor Restarted
CTITRIGOUT[0] Processor debug request Acknowledged by the debugger writing to the CTIINTACK register

Note:

  • After the processor is halted using CTI Trigger Output 0, the Processor Debug Request signal remains asserted. The debugger must write to CTIINTACK to clear the halting request before restarting the processor.
  • After asserting an interrupt using the CTI Trigger Output 1 or 2, the Interrupt Service Routine (ISR) must clear the interrupt request by writing to the CTI Interrupt Acknowledge, CTIINTACK.
  • Interrupt requests from the CTI to the system are only asserted when invasive debug is enabled in the processor.

If the CTI is not included in the processor, the trigger signals are tied off internally and the cross trigger functionality between the processor, MTB and ETM is not available.

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