C2.1.1 ITM register summary table

The following table shows the ITM registers whose implementation is specific to this processor.

Other registers are described in the Armv8‑M Architecture Reference Manual.

Depending on the implementation of your processor, the ITM registers might not be present. Any register that is configured as not present reads as zero.


  • You must enable TRCENA of the Debug Exception and Monitor Control Register before you program or use the ITM.
  • If the ITM stream requires synchronization packets, you must configure the synchronization packet rate in the DWT.

Table C2-1 ITM register summary

Address Name Type Reset Description



ITM_STIM0- ITM_STIM31 RW - Stimulus Port Registers 0-31
0xE0000E00 ITM_TER RW 0x00000000 Trace Enable Register
0xE0000E40 ITM_TPR RW 0x00000000 ITM Trace Privilege Register
0xE0000E80 ITM_TCR RW 0x00000000 Trace Control Register
0xE0000EF0 INT_ATREADY RO 0x00000000 Integration Mode: Read ATB Ready
0xE0000EF8 INT_ATVALID WO 0x00000000 Integration Mode: Write ATB Valid
0xE0000F00 ITM_ITCTRL RW 0x00000000 Integration Mode Control Register
0xE0000FCC ITM_DEVTYPE RW 0x00000043 ITM CoreSight Device Type Register
0xE0000FBC ITM_DEVARCH RO 0x47701A01 ITM CoreSight Device Architecture Register
0xE0000FD0 ITM_PIDR4 RO 0x00000004 Peripheral identification registers
0xE0000FD4 ITM_PIDR5 RO 0x00000000 Peripheral identification register
0xE0000FD8 ITM_PIDR6 RO 0x00000000 Peripheral identification register
0xE0000FDC ITM_PIDR7 RO 0x00000000 Peripheral identification register
0xE0000FE0 ITM_PIDR0 RO 0x00000021 Peripheral identification register
0xE0000FE4 ITM_PIDR1 RO 0x000000BD Peripheral identification register
0xE0000FE8 ITM_PIDR2 RO 0x0000000B Peripheral identification register
0xE0000FEC ITM_PIDR3 RO 0x00000000a Peripheral identification register
0xE0000FF0 ITM_CIDR0 RO 0x0000000D Component identification register
0xE0000FF4 ITM_CIDR1 RO 0x00000090 Component identification register
0xE0000FF8 ITM_CIDR2 RO 0x00000005 Component identification register
0xE0000FFC ITM_CIDR3 RO 0x000000B1 Component identification register


ITM registers are fully accessible in privileged mode. In user mode, all registers can be read, but only the Stimulus registers and Trace Enable registers can be written, and only when the corresponding Trace Privilege Register bit is set. Invalid user mode writes to the ITM registers are discarded. When the Armv8‑M Security Extension is included in the Cortex®‑M33 processor, writes to the Stimulus registers from the software running in Secure state are ignored if Secure non-invasive debug authentication is not enabled.
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