B5.1 About the FPU

The Cortex®‑M33 FPU is an implementation of the single precision variant of the Armv8‑M Floating-point extension, FPv5 architecture. It provides floating-point computation functionality that is compliant with the ANSI/IEEE Std 754-2008, IEEE Standard for Binary Floating-Point Arithmetic, referred to as the IEEE 754 standard.

The FPU supports all single-precision data-processing instructions and data types described in the Armv7‑M Architecture Reference Manual.

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