B5.3.1 Floating-point system registers

The following table shows a summary of the FP system registers in the Cortex®‑M33 processor, where FPU is included.

All Cortex‑M33 FPU registers are described in the Armv8‑M Architecture Reference Manual.

Table B5-1 FPU register summary

Address Name Type Reset value Processor security state Description
0xE000EF34 FPCCR RW 0xC0000004 Secure FP Context Control Register (S)
0xC0000000 Non-secure FP Context Control Register (NS)
0xE002EF34 FPCCR_NS RW 0xC0000000 Secure FP Context Control Register (NS)
- Non-secure RAZ/WI
0xE000EF38 FPCAR RW 0x00000000 Secure FP Context Address Register (S)
- Non-secure FP Context Address Register (NS)
0xE002EF38 FPCAR_NS RW 0x00000000 Secure FP Context Address Register (NS)
- Non-secure RAZ/WI
0xE000EF3C FPDSCR RW 0x00000000 Secure FP Default Status Control Register (S)
- Non-secure FP Default Status Control Register (NS)
0xE002EF3C FPDSCR_NS RW 0x00000000 Secure FP Default Status Control Register (NS)
- Non-secure RAZ/WI
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