C.8 Memory access and address space

In the Armv8‑M architecture, the following conditions apply.

  • Any access to memory from a load or store instruction or an instruction fetch which overflows the 32-bit address space is unpredictable. In the Cortex®‑M33 processor, these accesses wrap around to addresses at the start of memory.
  • Any unaligned access that is not faulted by the alignment restrictions and accesses Device memory has unpredictable behavior. In the Cortex‑M33 processor, accesses of this type generate an UNALIGNED UsageFault exception.
  • For any access X, the bytes accessed by X must all have the same memory type attribute, otherwise the behavior of the access is unpredictable. That is, an unaligned access that spans a boundary between different memory types is unpredictable. In the Cortex‑M33 processor, each part of an access to a different 32-byte aligned region is dealt with independently. If an MPU is included in the processor, each access to a different 32-byte region makes a new MPU lookup. If an MPU is not included, then the behavior of the associated background region is taken into account.
  • For any two memory accesses X and Y that are generated by the same instruction, the bytes accessed by X and Y must all have the same memory type attribute otherwise the results are unpredictable. For example, an LDC, LDM, LDRD, STC, STM, STRD, VSTM, VLDM, VPUSH, VPOP, VLDR, or VSTR that spans a boundary between Normal and Device memory is unpredictable. In the Cortex‑M33 processor, each part of access to a different 32-byte aligned region is dealt with independently. If an MPU is included in the processor, each access to a different 32-byte aligned region makes a new MPU lookup. If an MPU is not included, then the behavior of the associated background region is taken into account.
  • Any instruction fetch must only access Normal memory. If it accesses Device memory, the result is unpredictable. For example, instruction fetches must not be performed to an area of memory that contains read-sensitive devices because there is no ordering requirement between instruction fetches and explicit accesses. In the Cortex‑M33 processor, fetches to Device memory is sent out to the system, indicated on the AHB interface as Device, unless the memory region is marked with the Execute Never (XN) memory attribute.
  • If the Armv8‑M Security Extension is implemented, the behavior of sequential instruction fetches that cross from Non-secure to secure memory and fulfill the secure entry criteria specified in the architecture, including the presence of a Secure Gateway ( SG) instruction at the boundary of the secure memory area, is constrained unpredictable. In the Cortex‑M33 processor, this results in the transition to Secure state.
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