B6.5 Configuring which coprocessors are included in Secure and Non-secure states

If the Cortex®‑M33 processor is configured with the Armv8‑M Security extension, then it can support systems where coprocessors are only accessible from Secure state or from both Secure and Non-secure states.

Software can discover which coprocessors are available by accessing the CPACR and NSACR registers in the SCS memory region as documented in the Armv8‑M Architecture Reference Manual.

The following table shows the relationship between the coprocessor security type and the access control registers.

Table B6-2 Coprocessor security type and access control registers

Coprocessor n security type CPACR[2n+1:2n] NSACR[n]
From Secure From Non-secure
Not present RAZ/WI RAZ/WI RAZ/WI
Available in Secure only RW, reset to 0 RAZ/WI RAZ/WI
Available in Secure and Non-secure RW, reset to 0 RW, reset to 0 UNKNOWN


  • From coprocessors which can be accessed in Secure and Non-secure state the Secure software can further restrict access from Non-secure by using the NSACR register.
  • If the Cortex‑M33 processor is not configured with the Armv8‑M Security Extension, CPACR[2n+1:2n] is RW. If coprocessor n is available, NSACR is always RAZ/WI.

Using a coprocessor instruction for a coprocessor which is not accessible in the current security state results in a NOCP UsageFault exception.

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