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If the Cortex®‑M33 processor is configured with the Armv8‑M Security extension, then it can support systems where coprocessors are only accessible from Secure state or from both Secure and Non-secure states.
Software can discover which coprocessors are available by accessing the CPACR and NSACR registers in the SCS memory region as documented in the Armv8‑M Architecture Reference Manual.
The following table shows the relationship between the coprocessor security type and the access control registers.
Table B6-2 Coprocessor security type and access control registers
|Coprocessor n security type||CPACR[2n+1:2n]||NSACR[n]|
|From Secure||From Non-secure|
|Available in Secure only||RW, reset to 0||RAZ/WI||RAZ/WI|
|Available in Secure and Non-secure||RW, reset to 0||RW, reset to 0||UNKNOWN|
Using a coprocessor instruction for a coprocessor which is not accessible in the current security state results in a NOCP UsageFault exception.