C.6 Stack limit checking

The Armv8‑M architecture defines the instructions which are subject to stack limit checking when operating on SP.

It states that it is unknown whether a stack limit check is performed on any use of the SP that was unpredictable in Armv6-M and Armv7-M. In the Cortex®‑M33 processor, these unpredictable cases are when R13 is used as a general purpose register in instructions. In these circumstances, the processor generates an UNDEFINSTR UsageFault exception.

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