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The following figure shows the main functional blocks in the Cortex®‑M33
The Debug Port (DP)s and Access Port (AP) are compliant with ADIv5.2 architecture. An overview of each is as follows:
The SW-DP implements the Serial Wire debug interface and is compliant with DP architecture version 2 and Serial Wire protocol version 2.
The AHB-AP is an AHB master interface that is intended to be directly connected to the Cortex‑M33 processor D-AHB port. It is compliant with the MEM-AP definition and performs 8-bit, 16-bit, and 32-bit accesses.
The Dormant mode, and the switching to and from the Dormant mode, is supported in all configurations.