A.2 Functional description

The following figure shows the main functional blocks in the Cortex®‑M33

Figure A-2 Cortex‑M33 block diagram
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.

The Debug Port (DP)s and Access Port (AP) are compliant with ADIv5.2 architecture. An overview of each is as follows:

The JTAG-DP implements the JTAG debug interface and is compliant with DP architecture version 1.

The SW-DP implements the Serial Wire debug interface and is compliant with DP architecture version 2 and Serial Wire protocol version 2.

The SWJ-DP implements both the JTAG-DP and SW-DP. The SWJ-DP provides a mechanism to dynamically switch between the debug ports as described in Arm® Debug Interface Architecture Specification, ADIv5.0 to ADIv5.2.

The AHB-AP is an AHB master interface that is intended to be directly connected to the Cortex‑M33 processor D-AHB port. It is compliant with the MEM-AP definition and performs 8-bit, 16-bit, and 32-bit accesses.

The Dormant mode, and the switching to and from the Dormant mode, is supported in all configurations.

Non-ConfidentialPDF file icon PDF version100230_0004_00_en
Copyright © 2016–2018 Arm Limited or its affiliates. All rights reserved.