Arm Cortex‑M33 Processor Technical Reference Manual : A.3.1 AHB-AP register summary

The following table shows the AHB-AP register summary.

Table A-2 AHB-AP register summary

Offset	Type	Reset value	Name
`0x00`	RW	`0x03000000`	AHB-AP Control/Status Word register, CSW, 0x00
`0x04`	RW	-	AHB-AP Transfer Address Register, TAR, 0x04
`0x08`	-	-	Reserved, RAZ/SBZP
`0x0C`	RW	-	AHB-AP Data Read/Write register, DRW, 0x0C
`0x10`	RW	-	AHB-AP Banked Data registers, BD0-BD03, 0x10-0x1C
`0x14`	RW	-
`0x18`	RW	-
`0x1C`	RW	-
`0x20`-`0xF3`	-	-	Reserved, RAZ/SBZP
`0xF4`	RO	`0x00000000`	AHB-AP Configuration register, CFG, 0xF4
`0xF8`	RO	implementation defined	AHB-AP Debug Base Address register, ROM, 0xF8
`0xFC`	RO	`0x04770051`	AHB-AP Identification Register, IDR, 0xFC

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