A.3.2 Debug port register summary

The following table shows the Cortex®‑M33 DP registers, and summarizes which registers are implemented in the JTAG-DP and which are implemented in the SW-DP.

Table A-3 Debug port register summary

Name JTAG‑DP SW-DP Description
ABORT Yes Yes AP Abort register. See AP Abort register, ABORT.
IDCODE Yes No ID Code register. See Identification Code register, IDCODE.
DPIDR Yes Yes Debug Port Identification register. See Debug Port Identification Register, DPIDR.
CTRL/STAT Yes Yes Control/Status register. See Control/Status register, CTRL/STAT.
SELECT Yes Yes AP Select register. See AP Select register, SELECT.
RDBUFF Yes Yes Read Buffer register. See Read Buffer register, RDBUFF.
EVENTSTAT No Yes Event Status register. See Event Status register, EVENTSTAT.
DLCR No Yes Data Link Control Register. See Data Link Control Register, DLCR (SW-DP only).
TARGETID No Yes Target Identification register. See Target Identification register, TARGETID (SW-DP only).
DLPIDR No Yes Data Link Protocol Identification Register. See Data Link Protocol Identification Register, DLPIDR (SW-DP only).
RESEND No Yes Read Resend register. See Read Resend register, RESEND (SW-DP only).
IR Yes No Instruction Register. See Arm® Debug Interface Architecture Specification, ADIv5.0 to ADIv5.2 for more information.
BYPASS Yes No Bypass register. See Arm® Debug Interface Architecture Specification, ADIv5.0 to ADIv5.2 for more information.
DPACC Yes No DP Access register. See Arm® Debug Interface Architecture Specification, ADIv5.0 to ADIv5.2 for more information.
APACC Yes No AP Access register. See Arm® Debug Interface Architecture Specification, ADIv5.0 to ADIv5.2 for more information.
Non-ConfidentialPDF file icon PDF version100230_0004_00_en
Copyright © 2016–2018 Arm Limited or its affiliates. All rights reserved.