|Home > Appendices > Trace Port Interface Unit > About the TPIU|
The Cortex®‑M33 TPIU is an optional component that bridges between the on-chip trace data from the ETM and the ITM, with separate IDs, to a data stream.
The Cortex‑M33 TPIU encapsulates IDs where required, and an external Trace Port Analyzer (TPA) captures the data stream.
The Cortex‑M33 TPIU is specially designed for low-cost debug. If your implementation requires the additional features, like those in the CoreSight SoC-400 TPIU, your implementation can replace the Cortex‑M33 TPIU with other CoreSight components.
In this chapter, the term TPIU refers to the Cortex‑M33 TPIU. For information about the CoreSight SoC-400 TPIU, see the Arm® CoreSight™ SoC-400 Technical Reference Manual.