B.3 TPIU programmers model

The following table shows the TPIU registers. Depending on the implementation of your processor, the TPIU registers might not be present and the CoreSight TPIU might be present instead. Any register that is configured as not present reads as zero.

Note:

Arm® recommends that the TPIU is only reprogrammed before any data has been presented on either ATB slave port and either:

  • After both ATRESETn and TRESETn have been applied.
  • After a flush has been completed using FFCR.FOnMan.

If this is not followed, reprogramming can lead to either momentary or permanent data corruption that might require ATRESETn and TRESETn to be applied.

Table B-1 TPIU registers

Address Name Type Reset Description
0xE0040000 TPIU_SSPSR RO -a Supported Parallel Port Size Register
0xE0040004 TPIU_CSPSR RW 0x01 Current Parallel Port Size Register
0xE0040010 TPIU_ACPR RW 0x0000 B.3.1 Asynchronous Clock Prescaler Register
0xE00400F0 TPIU_SPPR RW 0x01 Selected Pin Protocol Register
0xE0040300 TPIU_FFSR RO 0x08 B.3.2 Formatter and Flush Status Register
0xE0040304 TPIU_FFCR RW 0x102 B.3.3 Formatter and Flush Control Register
0xE0040308 TPIU_PSCR RW 0x00 TPIU Periodic Synchronization Control Registerb
0xE0040EE8 TRIGGER RO 0x0 B.3.4 TRIGGER Register
0xE0040EEC ITFTTD0 RO 0x--000000 B.3.5 Integration Test FIFO Test Data 0 Register
0xE0040EF0 ITATBCTR2 RW 0x0 B.3.6 Integration Test ATB Control Register 2
0xE0040EF8 ITATBCTR0 RO 0x0 B.3.8 Integration Test ATB Control 0 Register
0xE0040EFC ITFTTD1 RO 0x--000000 B.3.7 Integration Test FIFO Test Data 1 Register
0xE0040F00 ITCTRL RW 0x0 B.3.9 Integration Mode Control
0xE0040FA0 CLAIMSET RW 0xF Claim tag set
0xE0040FA4 CLAIMCLR RW 0x0 Claim tag clear
0xE0040FC8 DEVID RO 0xCA0/0xCA1 B.3.10 Device Configuration Register
0xE0040FCC DEVTYPE RO 0x11 B.3.11 Device Type Identifier Register
0xE0040FD0 PIDR4 RO 0x04 Peripheral identification registers
0xE0040FD4 PIDR5 RO 0x00
0xE0040FD8 PIDR6 RO 0x00
0xE0040FDC PIDR7 RO 0x00
0xE0040FE0 PIDR0 RO 0x21
0xE0040FE4 PIDR1 RO 0xBD
0xE0040FE8 PIDR2 RO 0x0B
0xE0040FEC PIDR3 RO -c
0xE0040FF0 CIDR0 RO 0x0D Component identification registers
0xE0040FF4 CIDR1 RO 0x90
0xE0040FF8 CIDR2 RO 0x05
0xE0040FFC CIDR3 RO 0xB1

The following sections describe the TPIU registers whose implementation is specific to this processor. The Formatter, Integration Mode Control, and Claim Tag registers are described in the CoreSight™ Components Technical Reference Manual. Other registers are described in the Armv8‑M Architecture Reference Manual.

a The value at reset is tied to the MAXPORTSIZE configuration tie off.
b

The Synchronization Counter counts up to a maximum of 2^16 bytes, where the TPIU_PSCR.PSCount value determines the reload value of Synchronization Counter, as 2 to the power of the programmed value.

The TPIU_PSCR.PSCount value has a range between 0b100 and 0b10000, any attempt to program register outside the range causes the Synchronization Counter to become disabled.

c The value at reset is ECOREVNUM value.
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