B6.3 Usage restrictions

The following restrictions apply when the Cortex®‑M33 processor uses coprocessor instructions:

  • The LDC(2) or STC(2) instructions are not supported. If these are included in software with the <coproc> field set to a value between 0-7 and the coprocessor is present and enabled in the appropriate fields in the CPACR/NSACR registers, the Cortex‑M33 processor always attempts to take an Undefined instruction (UNDEFINSTR) UsageFault exception.
  • The processor register fields for data transfer instructions must not include the stack pointer (Rt = 0xD), this encoding is unpredictable in the Armv8‑M architecture and results in an UNDEFINSTR UsageFault exception in Cortex‑M33 if the coprocessor is present and enabled in the CPACR/NSACR registers.
  • If any coprocessor instruction is executed when the corresponding coprocessor is either not present or disabled in the CPACR/NSACR register, the Cortex‑M33 processor always attempts to take a No coprocessor (NOCP) UsageFault exception.
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