C.7 UNPREDICTABLE instructions within an IT block

Instructions executed in an IT block which change the PC are architecturally unpredictable unless they are the last instruction in the block.

In the Cortex®‑M33 processor:

  • Conditional branch instructions (Bcond label) always generate an unconditional UNDEFINSTR UsageFault exception.
  • unconditional branch instructions (B label) which are not the last instructions in the IT block generate an unconditional UNDEFINSTR UsageFault exception.
  • Branch with link instructions (BL label) which are not the last instructions in the IT block generate an unconditional UNDEFINSTR UsageFault exception. BLX PC is always unpredictable and generates an UNDEFINSTR UsageFault exception.
  • Branch and exchange instructions (BX Rm) which are not the last instructions in the IT block generate an unconditional UNDEFINSTR UsageFault exception.
  • Compare and Branch instructions (CBNZ and CBZ) always generate an unconditional UNDEFINSTR UsageFault exception.
  • Table branch instructions (TBB and TBH) which are not the last instructions in the IT block generate an unconditional UNDEFINSTR Usage Fault exception.
  • An IT instruction inside another IT block always generates an unconditional UNDEFINSTR UsageFault exception.
  • Data processing instructions which have PC as the destination register and are not architecturally unpredictable outside an IT block generate an unconditional UNDEFINSTR UsageFault exception unless they are the last instruction of the IT block.
  • Load instructions (LDR, LDM, and POP) which have PC as the destination register and are not architecturally unpredictable outside an IT block generate an unconditional UNDEFINSTR UsageFault exception unless they are the last instruction of the IT block.
  • If the Armv8‑M floating-point extension is included and one of the following instructions is executed in an IT block, the instruction behaves as a regular conditional instruction according to the position of the instruction in the IT block:
    • VCVTA.
    • VCVTN.
    • VCVTP.
    • VCVTM.
    • VMAXNM.
    • VMINNM.
    • VRINTA.
    • VRINTN.
    • VRINTP.
    • VRINTM.
    • VSEL.
  • Change Processor State instructions (CPS) always generate an unconditional UNDEFINSTR UsageFault exception.
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