C.4 Register list in load and store multiple instructions

Load and Store Multiple instructions (LDM, STM, PUSH, POP VLDM, and VSTM) transfer multiple registers to and from consecutive memory locations using an address from a base register, which can be optionally written back when the operation is complete.

The registers are selected from a list encoded in the instruction. Some of these encodings are unpredictable.

In the Cortex®‑M33 processor:

  • If the number of registers loaded is zero, then the instruction is a No Operation (NOP).
  • If the number of registers loaded is one, the single register is loaded.
  • If R13 is specified in the list, an UNDEFINSTR UsageFault exception is generated.
  • For a Load Multiple, if PC is specified in the list and the instructions is in an IT block and is not the final instruction, an unconditional UNDEFINSTR UsageFault exception is generated.
  • For a Store Multiple instruction, if PC is specified in the list an UNDEFINSTR UsageFault exception is generated.
  • For a Load Multiple instruction, if base writeback is specified and the register to be written back is also in the list to be loaded, the instruction performs all the loads in the specified addressing mode and the register being written back takes the loaded value.
  • For a Store Multiple instruction, if base writeback is specified and the register to be written back is also in the list to be stored, the value stored is the initial base register value. The base register is written back with the expected updated value.
  • For a floating-point Load or Store Multiple instruction, VLDM, VSTM VPUSH, and VPOP if the register list extends beyond S31 or D15, then the Cortex‑M33 processor generates an UNDEFINSTR UsageFault exception.
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