B2.1 Identification register summary

Identification registers allow software to determine the features and functionality available in the implemented processor.

Each of these registers is 32 bits wide. The following table shows the identification registers.

Note:

If the Armv8‑M Security Extension is not included, then only the Non-secure entries are available and the entire alias space is RAZ/WI.

Table B2-1 Identification register summary

Address Register Type Processor security state Reset value Description
0xE000ED00 CPUID RO Secure 0x410FD214 CPUID Base Register
Non-secure
0xE002ED00 CPUID_NS RO Secure CPUID Base Register (NS)
Non-secure   RAZ/WI
0xE000ED40 ID_PFR0 RO Secure 0x00000030 Processor Feature Register 0
Non-secure
0xE002ED40 ID_PFR0_NS RO Secure Processor Feature Register 0 (NS)
Non-secure   RAZ/WI
0xE000ED44 ID_PFR1 RO Secure 0x000002x0c Processor Feature Register 1
Non-secure
0xE002ED44 ID_PFR1_NS RO Secure Processor Feature Register 1 (NS)
Non-secure   RAZ/WI
0xE000ED48 ID_DFR0 RO Secure 0x00200000

b

Debug Feature Register 0
Non-secure
0xE002ED48 ID_DFR0_NS RO Secure Debug Feature Register 0 (NS)
Non-secure   RAZ/WI
0xE000ED4C ID_AFR0 RO Secure 0x00000000 Auxiliary Feature Register 0
Non-secure
0xE002ED4C ID_AFR0_NS RO Secure Auxiliary Feature Register 0 (NS)
Non-secure   RAZ/WI
0xE000ED50 ID_MMFR0 RO Secure 0x00101F40 Memory Model Feature Register 0
Non-secure
0xE002ED50 ID_MMFR0_NS RO Secure Memory Model Feature Register 0 (NS)
Non-secure   RAZ/WI
0xE000ED54 ID_MMFR1 RO Secure 0x00000000 Memory Model Feature Register 1
Non-secure
0xE002ED54 ID_MMFR1_NS RO Secure Memory Model Feature Register 1 (NS)
Non-secure   RAZ/WI
0xE000ED58 ID_MMFR2 RO Secure 0x01000000 Memory Model Feature Register 2
Non-secure
0xE002ED58 ID_MMFR2_NS RO Secure Memory Model Feature Register 2 (NS)
Non-secure   RAZ/WI
0xE000ED5C ID_MMFR3 RO Secure 0x00000000 Memory Model Feature Register 3
Non-secure
0xE002ED5C ID_MMFR3_NS RO Secure Memory Model Feature Register 3 (NS)
Non-secure   RAZ/WI
0xE000ED60 ID_ISAR0 RO Secure

0x011x1110e

Instruction Set Attributes Register 0
Non-secure
0xE002ED60 ID_ISAR0_NS RO Secure Instruction Set Attributes Register 0 (NS)
Non-secure   RAZ/WI
0xE000ED64 ID_ISAR1 RO Secure

0x0221x000f

Instruction Set Attributes Register 1
Non-secure
0xE002ED64 ID_ISAR1_NS RO Secure Instruction Set Attributes Register 1 (NS)
Non-secure   RAZ/WI
0xE000ED68 ID_ISAR2 RO Secure

0x20xx2232f

Instruction Set Attributes Register 2
Non-secure
0xE002ED68 ID_ISAR2_NS RO Secure Instruction Set Attributes Register 2 (NS)
Non-secure   RAZ/WI
0xE000ED6C ID_ISAR3 RO Secure

0x011111xxf

Instruction Set Attributes Register 3
Non-secure
0xE002ED6C ID_ISAR3_NS RO Secure Instruction Set Attributes Register 3 (NS)
Non-secure   RAZ/WI
0xE000ED70 ID_ISAR4 RO Secure 0x01310132 Instruction Set Attributes Register 4
Non-secure
0xE002ED70 ID_ISAR4_NS RO Secure Instruction Set Attributes Register 4 (NS)
Non-secure   RAZ/WI
0xE000ED78 CLIDR RO Secure 0x00000000 Cache Level ID Register
Non-secure
0xE002ED78 CLIDR _NS RO Secure Cache Level ID Register (NS)
Non-secure   RAZ/WI
0xE000ED7C CTR RO Secure 0x8000C000 Cache Type Register
Non-secure
0xE002ED7C CTR_NS RO Secure Cache Type Register (NS)
Non-secure   RAZ/WI
0xE000EF40 MVFR0 RO Secure 0x10110021d Media and VFP Feature Register 0
Non-secure
0xE002EF40 MVFR0_NS RO Secure Media and VFP Feature Register 0 (NS)
Non-secure   RAZ/WI
0xE000EF44 MVFR1 RO Secure 0x11000011d Media and VFP Feature Register 1
Non-secure
0xE002EF44 MVFR1_NS RO Secure Media and VFP Feature Register 1 (NS)
Non-secure   RAZ/WI
0xE000EF48 MVFR2 RO Secure 0x00000040d Media and VFP Feature Register 2
Non-secure
0xE002EF48 MVFR2_NS RO Secure Media and VFP Feature Register 2 (NS)
Non-secure   RAZ/WI
0xE000EFD0 PIDR4 RO Secure 0x00000004 CoreSight Peripheral ID Register 4
Non-secure
0xE002EFD0 PIDR4_NS RO Secure CoreSight Peripheral ID Register 4 (NS)
Non-secure   RAZ/WI
0xE000EFD4 PIDR5 RO Secure 0x00000000 CoreSight Peripheral ID Register 5
Non-secure
0xE002EFD4 PIDR5_NS RO Secure CoreSight Peripheral ID Register 5 (NS)
Non-secure   RAZ/WI
0xE000EFD8 PIDR6 RO Secure 0x00000000 CoreSight Peripheral ID Register 6
Non-secure
0xE002EFD8 PIDR6_NS RO Secure CoreSight Peripheral ID Register 6 (NS)
Non-secure   RAZ/WI
0xE000EFDC PIDR7 RO Secure 0x00000000 CoreSight Peripheral ID Register 7
Non-secure
0xE002EFDC PIDR7_NS RO Secure CoreSight Peripheral ID Register 7 (NS)
Non-secure   RAZ/WI
0xE000EFE0 PIDR0 RO Secure 0x00000021 CoreSight Peripheral ID Register 0
Non-secure
0xE002EFE0 PIDR0_NS RO Secure CoreSight Peripheral ID Register 0 (NS)
Non-secure   RAZ/WI
0xE000EFE4 PIDR1 RO Secure 0x000000BD CoreSight Peripheral ID Register 1
Non-secure
0xE002EFE4 PIDR1_NS RO Secure CoreSight Peripheral ID Register 1 (NS)
Non-secure   RAZ/WI
0xE000EFE8 PIDR2 RO Secure 0x0000000B CoreSight Peripheral ID Register 2
Non-secure
0xE002EFE8 PIDR2_NS RO Secure CoreSight Peripheral ID Register 2 (NS)
Non-secure   RAZ/WI
0xE000EFEC PIDR3 RO Secure 0x00000000a CoreSight Peripheral ID Register 3
Non-secure
0xE002EFEC PIDR3_NS RO Secure CoreSight Peripheral ID Register 3 (NS)
Non-secure   RAZ/WI
0xE000EFF0 CIDR0 RO Secure 0x0000000D CoreSight Component ID Register 0
Non-secure
0xE002EFF0 CIDR0_NS RO Secure CoreSight Component ID Register 0 (NS)
Non-secure   RAZ/WI
0xE000EFF4 CIDR1 RO Secure 0x00000090 CoreSight Component ID Register 1
Non-secure
0xE000EFF4 CIDR1_NS RO Secure CoreSight Component ID Register 1 (NS)
Non-secure   RAZ/WI
0xE002EFF8 CIDR2 RO Secure 0x00000005 CoreSight Component ID Register 2
Non-secure
0xE002EFF8 CIDR2_NS RO Secure CoreSight Component ID Register 2 (NS)
Non-secure   RAZ/WI
0xE000EFFC CIDR3 RO Secure 0x000000B1 CoreSight Component ID Register 3
Non-secure
0xE002EFFC CIDR3_NS RO Secure CoreSight Component ID Register 3 (NS)
Non-secure   RAZ/WI
0xE000EFBC DEVARCH RO Secure 0x47702A04 CoreSight Device Architecture Register
Non-secure
0xE002EFBC DEVARCH_NS RO Secure CoreSight Device Architecture Register (NS)
Non-secure   RAZ/WI
a Dependent on the exact revision of the silicon as documented in Arm® CoreSight™ Architecture Specification v2.0.
b When minimal debug support is implemented, this value is 0x00000000.
c ID_PFR1[7:4] indicates support for the Armv8‑M Security Extension. ID_PFR1[7:4] reads as 0b0001 if the Security Extension is supported otherwise ID_PFR1[7:4] reads as 0b0000.
d When the FPU is not implemented, this value is 0x00000000.
e ID_ISAR0[19:16] depend on whether the external coprocessor interface is included in the processor.
f ID_ISAR1[15:12], ID_ISAR2[31:28], ID_ISAR2[23:16] and ID_ISAR3[7:0] depend on whether theArmv8‑M DSP extension is included in the processor.
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