B1.4 Memory model

The processor contains a bus matrix that arbitrates instruction fetches and memory accesses from the processor core between the external memory system and the internal System Control Space (SCS) and debug components.

Priority is usually given to the processor to ensure that any debug accesses are as non-intrusive as possible.

The system memory map is Armv8‑M Main Extension compliant, and is common both to the debugger and processor accesses.

The default memory map provides user and privileged access to all regions except for the Private Peripheral Bus (PPB). The PPB space is privileged access only.

The following table shows the default memory map. This is the memory map that is used by implementations without the optional MPUs, or when the included MPUs are disabled. The attributes and permissions of all regions, except that targeting the NVIC and debug components, can be modified using an implemented MPU.

Default memory map

Address Range (inclusive) Region Interface
0x00000000-0x1FFFFFFF Code Instruction and data accesses performed on C-AHB.
0x20000000-0x3FFFFFFF SRAM

Instruction and data accesses performed on S-AHB. Any attempt to execute instructions from the peripheral and external device region results in a MemManage fault.

0x40000000-0x5FFFFFFF Peripheral
0x60000000-0x9FFFFFFF External RAM
0xA0000000-0xDFFFFFFF External device
0xE0040000-0xE00FFFFF PPB

Reserved for system control and debug.

Cannot be used for exception vector tables. Data accesses are either performed internally or on EPPB. Accesses in the range:

Are handled within the processor.
Appear as APB transactions on the EPPB interface of the processor.

Any attempt to execute instructions from the region results in a MemManage fault.

0xE0100000-0xFFFFFFFF Vendor_SYS

Partly reserved for future processor feature expansion.

Any attempt to execute instructions from the region results in a MemManage fault.

Data accesses are performed on S-AHB

When the Armv8‑M Security Extension is included, the security level associated with an address is determined by either the internal Secure Attribution Unit (SAU) or an external Implementation Defined Attribution Unit (IDAU) in the system. Some internal peripherals have memory-mapped registers in the PPB region which are banked between Secure and Non-secure state. When the processor is in Secure state, software can access both the Secure and Non-secure versions of these registers. The Non-secure versions are accessed using an aliased address. If the Armv8‑M Security Extension is not included, all memory is treated as Non-secure.

See the Armv8‑M Architecture Reference Manual for more information about the memory model.

Non-ConfidentialPDF file icon PDF version100230_0004_00_en
Copyright © 2016–2018 Arm Limited or its affiliates. All rights reserved.