B1.6 Processor core registers summary

The following table shows the processor core register set summary. Each of these registers is 32 bits wide. When the Armv8‑M Security Extension is included, some of the registers are banked. The Secure view of these registers is available when the Cortex®‑M33 processor is in Secure state and the Non-secure view when Cortex‑M33 processor is in Non-secure state.

Table B1-1 Processor core register set summary

Name Description
R0-R12 R0-R12 are general-purpose registers for data operations.
MSP (R13)

The Stack Pointer (SP) is register R13. In Thread mode, the CONTROL register indicates the stack pointer to use, Main Stack Pointer (MSP) or Process Stack Pointer (PSP).

When the Armv8‑M Security Extension is included, there are two MSP registers in the Cortex‑M33 processor:
  • MSP_NS for the Non-secure state.
  • MSP_S for the Secure state.

When the Armv8‑M Security Extension is included, there are two PSP registers in the Cortex‑M33 processor:

  • PSP_NS for the Non-secure state.
  • PSP_S for the Secure state.
PSP (R13)
MSPLIM The stack limit registers limit the extent to which the MSP and PSP registers can descend respectively.

When the Armv8‑M Security Extension is included, there are two MSPLIM registers in the Cortex‑M33 processor:

  • MSPLIM_NS for the Non-secure state.
  • MSPLIM_S for the Secure state.

When the Armv8‑M Security Extension is included, there are two PSPLIM registers in the Cortex‑M33 processor:

  • PSPLIM_NS for the Non-secure state.
  • PSPLIM_S for the Secure state.
PSPLIM
LR (R14) The Link Register (LR) is register R14. It stores the return information for subroutines, function calls, and exceptions.
PC (R15) The Program Counter (PC) is register R15. It contains the current program address.
PSR

The Program Status Register (PSR) combines:

  • Application Program Status Register (APSR).
  • Interrupt Program Status Register (IPSR).
  • Execution Program Status Register (EPSR).

These registers provide different views of the PSR.

PRIMASK

The PRIMASK register prevents activation of exceptions with configurable priority. For information about the exception model the processor supports, see B1.7 Exceptions.

When the Armv8‑M Security Extension is included, there are two PRIMASK registers in the Cortex‑M33 processor:

  • PRIMASK_NS for the Non-secure state.
  • PRIMASK_S for the Secure state.
BASEPRI

The BASEPRI register defines the minimum priority for exception processing.

When the Armv8‑M Security Extension is included, there are two BASEPRI registers in the Cortex‑M33 processor:

  • BASEPRI_NS for the Non-secure state.
  • BASEPRI_S for the Secure state.
FAULTMASK

The FAULTMASK register prevents activation of all exceptions except for Non-Maskable Interrupt (NMI) and optionally Secure HardFault.

When the Armv8‑M Security Extension is included, there are two FAULTMASK registers in the Cortex‑M33 processor:

  • FAULTMASK_NS for the Non-secure state.
  • FAULTMASK_S for the Secure state.
CONTROL

The CONTROL register controls the stack used, and optionally the privilege level, when the processor is in Thread mode.

When the Armv8‑M Security Extension is included, there are two CONTROL registers in the Cortex‑M33 processor:

  • CONTROL_NS for the Non-secure state.
  • CONTROL_S for the Secure state.

Note:

See the Armv8‑M Architecture Reference Manual for information about the processor core registers and their addresses, access types, and reset values.
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