lbl.part B Functional description

Table of Contents

B1 Programmers Model
B1.1 About the programmers model
B1.2 Modes of operation and execution
B1.3 Instruction set summary
B1.4 Memory model
B1.4.1 Private Peripheral Bus
B1.4.2 Unaligned accesses
B1.5 Exclusive monitor
B1.6 Processor core registers summary
B1.7 Exceptions
B1.7.1 Exception handling and prioritization
B2 System Control
B2.1 Identification register summary
B2.2 Auxiliary Control Register
B2.3 CPUID Base Register
B3 Security Attribution and Memory Protection
B3.1 About security attribution and memory protection
B3.2 SAU register summary
B3.3 MPU register summary
B4 Nested Vectored Interrupt Controller
B4.1 NVIC programmers model
B4.1.1 NVIC register summary
B4.1.2 Interrupt Controller Type Register
B5 Floating-Point Unit
B5.1 About the FPU
B5.2 FPU functional description
B5.2.1 FPU views of the register bank
B5.2.2 Modes of operation
B5.2.3 Compliance with the IEEE 754 standard
B5.2.4 Exceptions
B5.3 FPU programmers model
B5.3.1 Floating-point system registers
B5.3.2 Low-power operation
B6 External coprocessors
B6.1 About external coprocessors
B6.2 Operation
B6.3 Usage restrictions
B6.4 Data transfer rates
B6.5 Configuring which coprocessors are included in Secure and Non-secure states
B6.6 Debug access to coprocessor registers usage constraints
B6.7 Exceptions and context switch
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