lbl.part D Appendices

Table of Contents

A Debug Access Port
A.1 About the Debug Access Port
A.1.1 Configuration options
A.2 Functional description
A.3 DAP register summary
A.3.1 AHB-AP register summary
A.3.2 Debug port register summary
A.4 DAP register descriptions
A.4.1 AHB-AP register descriptions
A.4.2 Debug port registers
B Trace Port Interface Unit
B.1 About the TPIU
B.2 TPIU functional description
B.2.1 TPIU Formatter
B.2.2 Serial Wire Output format
B.3 TPIU programmers model
B.3.1 Asynchronous Clock Prescaler Register
B.3.2 Formatter and Flush Status Register
B.3.3 Formatter and Flush Control Register
B.3.4 TRIGGER Register
B.3.5 Integration Test FIFO Test Data 0 Register
B.3.6 Integration Test ATB Control Register 2
B.3.7 Integration Test FIFO Test Data 1 Register
B.3.8 Integration Test ATB Control 0 Register
B.3.9 Integration Mode Control
B.3.10 Device Configuration Register
B.3.11 Device Type Identifier Register
C UNPREDICTABLE Behaviors
C.1 Use of instructions defined in architecture variants
C.2 Use of Program Counter - R15 encoding
C.3 Use of Stack Pointer - as a general purpose register R13
C.4 Register list in load and store multiple instructions
C.5 Exception-continuable instructions
C.6 Stack limit checking
C.7 UNPREDICTABLE instructions within an IT block
C.8 Memory access and address space
C.9 Load exclusive and Store exclusive accesses
C.10 Armv8-M MPU programming
C.11 Miscellaneous UNPREDICTABLE instruction behavior
D Revisions
D.1 Revisions
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