B5.2.4 Exceptions

The FPU sets the cumulative exception status flag in the FPSCR register as required for each instruction, in accordance with the FPv5 architecture. The FPU does not support exception traps.

The processor also has six output pins, each reflect the status of one of the cumulative exception flags:

FPIXCMasked floating-point inexact exception.
FPUFCMasked floating-point underflow exception.
FPOFCMasked floating-point overflow exception.
FPDZCMasked floating-point divide by zero exception.
FPIDCMasked floating-point input denormal exception.
FPIOCInvalid operation.

When a floating-point context is active, the stack frame is extended to accommodate the floating-point registers. To reduce the additional interrupt latency associated with writing the larger stack frame on exception entry, the processor supports lazy stacking. This means that the processor reserves space on the stack for the FP state, but does not save that state information to the stack unless the processor executes an FPU instruction inside the exception handler.

The lazy save of the FP state is interruptible by a higher priority exception. The FP state saving operation starts over after that exception returns.

See the Armv8‑M Architecture Reference Manual for more information.

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