B6.2 Operation

The following instruction types are supported:

  • Register transfer from the Cortex®‑M33 processor to the coprocessor MCR, MCRR, MCR2, MCRR2.
  • Register transfer from the coprocessor to the Cortex‑M33 processor MRC, MRRC, MRC2, MRRC2.
  • Data processing instructions CDP, CDP2.

Note:

The regular and extension forms of the coprocessor instructions for example, MCR and MCRR2, have the same functionality but different encodings.

The MRC and MRC2 instructions support the transfer of APSR.NZVC flags when the processor register field is set to PC, for example Rt == 0xF.

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