C.11 Miscellaneous UNPREDICTABLE instruction behavior

This section documents the behavior of the Cortex®‑M33 processor in a number of miscellaneous unpredictable instruction scenarios:

  • Load instructions which specify writeback of the base register are unpredictable if the base register to be written back matches the register to be loaded (Rn==Rt). In the Cortex‑M33 processor, the base register is updated to the loaded value.
  • Store instructions which specify writeback of the base register are unpredictable if the base register to be written back matches the register to be stored (Rn==Rt). In the Cortex‑M33 processor, the value stored is the initial base register value. The base register is then written back with the expected updated value.
  • Multiply and Multiply accumulate instructions which write a 64-bit result using two registers, SMULL, SMLAL, SMLALBB, SMLALBT, SMLALTB, SMLALTT, SMLALD, SMLALDX, SMLSLD, SMLSLDX, UMULL, and UMAAL are unpredictable if the two registers are the same (RdHi==RdLo). In the Cortex‑M33 processor, these cases generate an UNDEFINSTR UsageFault exception.
  • Floating-point instructions which transfer between two registers and either two single precision registers or one double precision register, VMOV Rt, Rt2, Dm and VMOV Rt, Rt2, Sm, Sm1 are unpredictable if the two registers are the same (Rt==Rt2). In the Cortex‑M33 processor, these cases generate an UNDEFINSTR UsageFault exception.
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