C.10 Armv8-M MPU programming
The Armv8‑M Protected Memory System Architecture (PMSA) includes a number of unpredictable cases when programming the MPU when it is included in an implementation.
In the Cortex®‑M33 processor:
- Setting MPU_CTRL.ENABLE to 0 and MPU_CTRL.HFNMIEA to 1 is unpredictable. This results in
all memory accesses using the default memory map including those from Exception
Handlers with a priority less than one.
- If MPU_RNR is written with a region number greater than the number of regions defined in the
MPU, then the value used is masked by one less than the number of regions
defined. For example:
The number of regions available can be read from MPU_TYPE.DREGION.
- The number of regions defined is given as num_regions. The value written
to MPU_RNR is given as v.
- num_regions=8 and v=9.
- The effective region used is given as 9 & (8-1); region 1.
- Setting MPU_RBAR.SH to 1 is unpredictable. This encoding is treated as Non-shareable.
- The Attribute fields (MPU_ATTR) of the MPU_MAIR0 and MPU_MAIR1 registers include some
encodings which are unpredictable.
- If MPU_ATTR[7:4]!=0 and MPU_ATTR[3:0]==0 is unpredictable, the attributes are
treated as Normal memory, Outer non-cacheable, Inner non-cacheable.
- If MPU_ATTR[7:4]==0 and MPU_ATTR[1:0]!=0 is unpredictable, the attributes are
treated as Device-nGnRE.
- The external AMBA AHB5 interface signals cannot distinguish between some of
the memory attribute encodings defined by the Armv8‑M PMSA:
- Normal transient memory is treated the same as Normal
- Device memory with gathering or Reordering attributes
(G, R) are always treated as non-Gathering and non-Reordering. Early
Write Acknowledgment attributes (E, nE) are supported on the Cortex‑M33