A2.3.8 Low-power state behavior

When the processor enters a low-power state, there is a delay before the resources to the ETM-M33 become inactive.

This permits the last instruction executed, to trigger a comparator, or update the counter, and the resultant event packet to be inserted in the specified trace stream. This event packet is presented on the trace bus before the ETM-M33 itself enters a low-power state.

If an event packet is generated for a different reason, it is not guaranteed to be output before the ETM-M33 enters a low-power state, but is traced when the processor leaves the low-power state, if the ETM-M33 logic is not reset before this can occur.

This low-power behavior can be disabled using TRCEVENTCTL1R.LPOVERRIDE bit, see B1.6 Event Control 0 Register. In this case, the ETM-M33 resources remain active.

Non-ConfidentialPDF file icon PDF versionARM 100232_0002_00_en
Copyright © 2016, 2017 ARM Limited or its affiliates. All rights reserved.