B1.1 Register summary

This section summarizes the ETM-M33 registers.

For full descriptions of the ETM-M33 registers, see:

  • The ARM® Embedded Trace Macrocell Architecture Specification ETMv4, for registers not described in this document.

Table B1-1 ETM-M33 register summary lists the ETM-M33 registers in numerical order and describes each register.

The register table includes additional information about each register:

  • The register access type. This is read-only, write-only, or read and write.
  • The base offset address of the register. The base offset of a register is always four times its register number. For information on the base address of the registers, see ARM®v8‑M Architecture Reference Manual.
  • Additional information about the implementation of the register, where appropriate.

Note:

  • Registers not listed here are not implemented. Reading a non-implemented register address returns 0. Writing to a non-implemented register address has no effect.
  • In the following table:

    • The Reset value column shows the value of the register immediately after an ETM-M33 reset. For read-only registers, every read of the register returns this value.

    • Access type is described as follows:

      RWRead and write.
      RORead only.
      WOWrite only.

All the ETM-M33 registers are 32 bits wide.

Table B1-1 ETM-M33 register summary

Register number

Base offset Name Type Reset value Description
1 0x004 TRCPRGCTLR RW 0x00000000 B1.2 Programming Control Register
3 0x00C TRCSTATR RO - B1.3 Status Register
4 0x010 TRCCONFIGR RW - B1.4 Trace Configuration Register
6 0x018 TRCAUXCTLRa RW - UNK/SBZP.
8 0x020 TRCEVENTCTL0R RW - B1.6 Event Control 0 Register
9 0x024 TRCEVENTCTL1R RW - B1.7 Event Control 1 Register
11 0x02C TRCSTALLCTLR RW - B1.8 Stall Control Register
12 0x030 TRCTSCTLR RW - B1.9 Global Timestamp Control Register
13 0x034 TRCSYNCPR RO 0xA B1.10 Synchronization Period Register
14 0x038 TRCCCCTLR RW - B1.11 Cycle Count Control Register
16 0x040 TRCTRACEIDR RW - B1.12 Trace ID Register
32 0x080 TRCVICTLR RW - B1.13 ViewInst Main Control Register
80-81

0x140

TRCCNTRLDVR0 RW - B1.14 Counter Reload Value Registers 0
96 0x180 TRCIDR8 RO 0x00000000 B1.15 ID Register 8-13
97 0x184 TRCIDR9 RO 0x00000000
99 0x18C TRCIDR11 RO 0x00000000
100 0x190 TRCIDR12 RO 0x00000001
101 0x194 TRCIDR13 RO 0x00000000
112 0x1C0 TRCIMSPEC0 RW 0x00000000 B1.16 Implementation Specific Register 0
120 0x1E0 TRCIDR0 RO 0x280006E1 B1.17 ID Register 0
121 0x1E4 TRCIDR1 RO 0x4100F421 B1.18 ID Register 1
122 0x1E8 TRCIDR2 RO 0x00000004 B1.19 ID Register 2
123 0x1EC TRCIDR3 RO 0x07090004b B1.20 ID Register 3
124 0x1F0 TRCIDR4 RO -c B1.21 ID Register 4
125 0x1F4 TRCIDR5 RO 0x90C70004 B1.22 ID Register 5
130-143

0x208-0x20C

TRCRSCTLR2-3 RW - B1.23 Resource Selection Registers 2-3
160 0x280 TRCSSCCR0 RW - B1.24 Single-shot Comparator Control Register 0
168 0x2A0 TRCSSCSR0 RW - B1.25 Single-shot Comparator Status Register 0
176 0x2C0 TRCSSPCICR0 RW - B1.26 Single-shot Processor Comparator Input Control Register
196 0x310 TRCPDCR RW 0x00000000 B1.27 Power Down Control Register
197 0x314 TRCPDSR RO 0x00000003 B1.28 Power Down Status Register
953 0xEE4 TRCITATBIDR RW - B1.29.1 Integration ATB Identification Register
957 0xEF4 TRCITIATBINR RO - B1.29.2 Integration Instruction ATB In Register
959 0xEFC TRCITIATBOUTR RW - B1.29.3 Integration Instruction ATB Out Register
960 0xF00 TRCITCTRL RW 0x00000000 B1.29.4 Integration Mode Control Register
1000 0xFA0 TRCCLAIMSET RW 0x0000000F B1.30 Claim Tag Set Register
1001 0xFA4 TRCCLAIMCLR RW 0x00000000 B1.31 Claim Tag Clear Register
1006 0xFB8 TRCAUTHSTATUS RO - B1.32 Authentication Status Register
1007 0xFBC TRCDEVARCH RO 0x47724A13 B1.33 Device Architecture Register
1010 0xFC8 TRCDEVID RO 0x00000000 B1.34 Device ID Register
1011 0xFCC TRCDEVTYPE RO 0x00000013 B1.35 Device Type Register
1012-1019

0xFD0-0xFEC

TRCPIDR0-7 RO - B1.36 Peripheral Identification Registers
1020-1023

0xFF0-0xFFC

TRCCIDR0-3 RO - B1.37 Component Identification Registers
This section contains the following subsections:
a The processor does not implement this register.
b Bits[30:27] are implementation dependent.
c
0x00114000For 4 comparator configuration.
0x00112000For 2 comparator configuration.
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