B1.17 ID Register 0

The TRCIDR0 indicates the tracing capabilities of the ETM-M33 instruction trace.

Usage constraints

There are no usage constraints.

Configurations
Available in all configurations.
Attributes
See the register summary in Table B1-1 ETM-M33 register summary and Table B1-5 Implementation specific and identification registers.

The following figure shows the TRCIDR0 bit assignments.

Figure B1-20 TRCIDR0 bit assignments
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The following table shows the TRCIDR0 bit assignments.

Table B1-30 TRCIDR0 bit assignments

Bits Name Function
[31:30] - res0.
[29] COMMOPT Indicates the meaning of the commit field in some packets:
1Commit mode 1.
[28:24] TSSIZE Global timestamp size:
0b01000Maximum of 64-bit global timestamp implemented.
[23:18] - res0.
[17] TRCEXDATA Indicates support for the tracing of data transfers for exceptions and exception returns:
0TRCVDCTLR.TRCEXDATA is not implemented.
[16:15] QSUPP Indicates Q element support:
0b00Q elements not supported.
[14] QFILT

res0.

[13:12] CONDTYPE Indicates how conditional results are traced:
0b00The trace unit indicates only if a conditional instruction passes or fails its condition code check.
[11:10] NUMEVENT Number of events supported in the trace:
0b01Two events supported.
[9] RETSTACK Return stack support:
1Two entry return stack implemented.
[8] - res0.
[7] TRCCCI Support for cycle counting in the instruction trace:
1Cycle counting in the instruction trace is implemented.
[6] TRCCOND Support for conditional instruction tracing:
1Conditional instruction tracing is implemented.
[5] TRCBB Support for branch broadcast tracing:
1Branch broadcast tracing is implemented.
[4:3] TRCDATA Support for tracing of data:
0b00Data tracing is not supported.
[2:1] INSTP0 Support for tracing of load and store instructions as P0 elements:
0b00Tracing of load and store instructions as P0 elements is not supported.
[0] -

res1.

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