B1.20 ID Register 3
The TRCIDR3 indicates certain aspects of the ETM-M33 configuration.
- Usage constraints
- There are no usage constraints.
- Available in all configurations.
- See the register summary in Table B1-1 ETM-M33 register summary and
Table B1-5 Implementation specific and identification registers.
The following figure shows the TRCIDR3 bit assignments.
Figure B1-23 TRCIDR3 bit assignments
The following table shows the TRCIDR3 bit assignments.
Table B1-33 TRCIDR3 bit assignments
||Indicates whether TRCSTALLCTLR.NOOVERFLOW is
|NOOVERFLOW is not implemented.
||Indicates the number of processors available for
tracing. This is driven from the ETM-M33
NUMPROC input pin,
reflecting system implementation:
|The trace unit can trace one processor.
||System support for stall control of the processor.
This is driven from the ETM-M33
SYSSTALL input pin,
reflecting the system implementation:
|System supports stall control of the processor.
This field is used with STALLCTL. Only when both SYSSTALL and
1 does the system
support stalling of the processor.
||Stall control support:
|TRCSTALLCTLR is implemented.
||Indicates trace synchronization period support:
|TRCSYNCPR is read-only for instruction trace only
configuration. The trace synchronization period is fixed.
||Indicates whether TRCVICTLR.TRCERR is implemented:
||Privilege levels implemented. One bit for each
|Privilege levels Thread and Handler are implemented.
||Minimum value which can be programmed to
TRCCCCTLR.THRESHOLD, defining the minimum cycle counting threshold.
|Minimum of four instruction trace cycles.