B1.20 ID Register 3

The TRCIDR3 indicates certain aspects of the ETM-M33 configuration.

Usage constraints
There are no usage constraints.
Available in all configurations.
See the register summary in Table B1-1 ETM-M33 register summary and Table B1-5 Implementation specific and identification registers.

The following figure shows the TRCIDR3 bit assignments.

Figure B1-23 TRCIDR3 bit assignments
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The following table shows the TRCIDR3 bit assignments.

Table B1-33 TRCIDR3 bit assignments

Bits Name Function
[31] NOOVERFLOW Indicates whether TRCSTALLCTLR.NOOVERFLOW is implemented:
0NOOVERFLOW is not implemented.
[30:28] NUMPROC Indicates the number of processors available for tracing. This is driven from the ETM-M33 NUMPROC input pin, reflecting system implementation:
0b000The trace unit can trace one processor.
[27] SYSSTALL System support for stall control of the processor. This is driven from the ETM-M33 SYSSTALL input pin, reflecting the system implementation:
1System supports stall control of the processor.

This field is used with STALLCTL. Only when both SYSSTALL and STALLCTL are 1 does the system support stalling of the processor.

[26] STALLCTL Stall control support:
1TRCSTALLCTLR is implemented.
[25] SYNCPR Indicates trace synchronization period support:
1TRCSYNCPR is read-only for instruction trace only configuration. The trace synchronization period is fixed.
[24] TRCERR Indicates whether TRCVICTLR.TRCERR is implemented:
1TRCERR is implemented.
[23:20] EXLEVEL_NS


[19:16] EXLEVEL_S Privilege levels implemented. One bit for each level.
0b1001Privilege levels Thread and Handler are implemented.
[15:12] - res0.
[11:0] CCITMIN Minimum value which can be programmed to TRCCCCTLR.THRESHOLD, defining the minimum cycle counting threshold.
0x4Minimum of four instruction trace cycles.
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