B1.24 Single-shot Comparator Control Register 0

The TRCSSCCR0 controls the single-shot comparator.

Usage constraints
There are no usage constraints.
Available in all configurations.
See the register summary in Table B1-1 ETM-M33 register summary and Table B1-7 Single-shot comparator registers.

The following figure shows the TRCSSCCR0 bit assignments.

Figure B1-27 TRCSSCCR0 bit assignments
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The following table shows the TRCSSCCR0 bit assignments.

Table B1-37 TRCSSCCR0 bit assignments

Bits Name Function
[31:25] - res0.
[24] RST

Enables the single-shot comparator resource to be reset when it occurs, to enable another comparator match to be detected:

1Reset enabled. Multiple matches can occur.
[23:20] - res0.
[19:16] ARC


[15:8] - res0.
[7:0] SAC


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