B1.24 Single-shot Comparator Control Register 0

The TRCSSCCR0 controls the single-shot comparator.

Usage constraints
There are no usage constraints.
Configurations
Available in all configurations.
Attributes
See the register summary in Table B1-1 ETM-M33 register summary and Table B1-7 Single-shot comparator registers.

The following figure shows the TRCSSCCR0 bit assignments.

Figure B1-27 TRCSSCCR0 bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


The following table shows the TRCSSCCR0 bit assignments.

Table B1-37 TRCSSCCR0 bit assignments

Bits Name Function
[31:25] - res0.
[24] RST

Enables the single-shot comparator resource to be reset when it occurs, to enable another comparator match to be detected:

1Reset enabled. Multiple matches can occur.
[23:20] - res0.
[19:16] ARC

RAZ/WI.

[15:8] - res0.
[7:0] SAC

RAZ/WI.

Non-ConfidentialPDF file icon PDF versionARM 100232_0002_00_en
Copyright © 2016, 2017 ARM Limited or its affiliates. All rights reserved.