B1.25 Single-shot Comparator Status Register 0

The TRCSSCSR0 indicates the status of the single-shot comparators. TRCSSCSR0 is sensitive to instruction addresses.

Usage constraints

There are no usage constraints.

Available in all configurations.
See the register summary in Table B1-1 ETM-M33 register summary and Table B1-7 Single-shot comparator registers.

The following figure shows the TRCSSCSR0 bit assignments.

Figure B1-28 TRCSSCSR0 bit assignments
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The following table shows the TRCSSCSR0 bit assignments.

Table B1-38 TRCSSCSR0 bit assignments

Bits Name Function

Single-shot status. This indicates whether any of the selected comparators have matched:

0Match has not occurred.
1Match has occurred at least once.

When programming ETM-M33, if TRCSSCCR0.RST is 0, the STATUS bit must be explicitly written to 0 to enable this single-shot comparator control.

[30:4] - res0.
[3] PC

Indicates that the Single-shot comparator is sensitive to processor comparator inputs:

1Single-shot comparator is sensitive to processor comparator inputs.
[2] DV

Data value comparator support:

0Single-shot data value comparisons not supported.
[1] DA

Data address comparator support:

0Single-shot data address comparisons not supported.
[0] INST

Instruction address comparator support:

0Single-shot instruction address comparisons not supported.
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