B1.7 Event Control 1 Register

The TRCEVENTCTL1R controls how the events selected by TRCEVENTCTL0R behave.

See B1.6 Event Control 0 Register.

Usage constraints
This register must always be programmed as part of the trace unit initialization.
Only accepts writes when the trace unit is disabled.
Available in all configurations.
See the register summary in Table B1-1 ETM-M33 register summary and Table B1-2 General control and ID registers.

The following figure shows the TRCEVENTCTL1R bit assignments.

Figure B1-5 TRCEVENTCTL1R bit assignments
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The following table shows the TRCEVENTCTL1R bit assignments.

Table B1-15 TRCEVENTCTL1R bit assignments

Bits Name Function
[31:13] - res0.
[12] LPOVERRIDE Low power state behavior override:
0Low power state behavior unaffected.
1Low power state behavior overridden. The resources and Event trace generation are unaffected by entry to a low power state.
[11] ATB ATB trigger enable:
0ATB trigger disabled.
1ATB trigger enabled.
[10:4] - res0
[3:2] - res0/WI
[1:0] INSTEN One bit per event, to enable generation of an event element in the instruction trace stream when the selected event occurs:
0Event does not cause an event element.
1Event causes an event element.
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