B1.7 Event Control 1 Register
The TRCEVENTCTL1R controls how the events selected by TRCEVENTCTL0R behave.
See B1.6 Event Control 0 Register.
- Usage constraints
- This register must always be programmed as part of the trace unit initialization.
- Only accepts writes when the trace unit is disabled.
- Available in all configurations.
- See the register summary in Table B1-1 ETM-M33 register summary and
Table B1-2 General control and ID registers.
The following figure shows the TRCEVENTCTL1R bit assignments.
Figure B1-5 TRCEVENTCTL1R bit assignments
The following table shows the TRCEVENTCTL1R bit assignments.
Table B1-15 TRCEVENTCTL1R bit assignments
|| Low power state behavior override:
|Low power state behavior unaffected.
|Low power state behavior overridden. The resources and Event
trace generation are unaffected by entry to a low power state.
|| ATB trigger enable:
|ATB trigger disabled.
|ATB trigger enabled.
|| One bit per event, to enable generation of an
event element in the instruction trace stream when the selected event occurs:
|Event does not cause an event element.
|Event causes an event element.