B1.8 Stall Control Register

The TRCSTALLCTLR enables ETM-M33 to stall the processor if the ETM-M33 FIFO goes over the programmed level to minimize risk of overflow.

Usage constraints
Only accepts writes when the trace unit is disabled.
This register must always be programmed as part of the trace unit initialization.
Configurations
Available in all configurations.
Attributes
See the register summary in Table B1-1 ETM-M33 register summary and Table B1-2 General control and ID registers.

The following figure shows the TRCSTALLCTLR bit assignments.

Figure B1-6 TRCSTALLCTLR bit assignments
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The following table shows the TRCSTALLCTLR bit assignments.

Table B1-16 TRCSTALLCTLR bit assignments

Bits Name Function
[31:11] - res0.
[10]

INSTPRIORITY

Prioritize instruction trace if instruction trace buffer space is less than LEVEL:
0The trace unit must not prioritize instruction trace.
1The trace unit can prioritize instruction trace.
[9]

-

res0.

[8] ISTALL Stall processor based on instruction trace buffer space:
0The trace unit must not stall the processor.
1The trace unit can stall the processor.
[7:4] - res0.
[3:0]

LEVEL

Threshold at which stalling becomes active. This provides four levels. This level can be varied to optimize the level of invasion caused by stalling, balanced against the risk of a FIFO overflow:
0b0000Zero invasion. This setting has a greater risk of a FIFO overflow
0b1111Maximum invasion occurs but there is less risk of a FIFO overflow.
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