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The TRCSTALLCTLR enables ETM-M33 to stall the processor if the ETM-M33 FIFO goes over the programmed level to minimize risk of overflow.
The following figure shows the TRCSTALLCTLR bit assignments.
The following table shows the TRCSTALLCTLR bit assignments.
Table B1-16 TRCSTALLCTLR bit assignments
| Prioritize instruction trace if instruction trace
buffer space is less than LEVEL:
|||ISTALL|| Stall processor based on instruction trace buffer
| Threshold at which stalling becomes active. This
provides four levels. This level can be varied to optimize the level of invasion
caused by stalling, balanced against the risk of a FIFO overflow: