B1.13 ViewInst Main Control Register

The TRCVICTLR controls instruction trace filtering.

Usage constraints
Only accepts writes when the trace unit is disabled.
Only returns stable data when TRCSTATR.PMSTABLE is 1.
Must be programmed, particularly to set the value of the SSSTATUS bit, that sets the state of the start-stop logic.
Configurations
Available in all configurations.
Attributes
See the register summary in Table B1-1 ETM-M33 register summary and Table B1-3 Trace filtering control register.

The following figure shows the TRCVICTLR bit assignments.

Figure B1-11 TRCVICTLR bit assignments
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The following table shows the TRCVICTLR bit assignments.

Table B1-21 TRCVICTLR bit assignments

Bits Name Function
[31:20] - res0.
[19:16] EXLEVEL_S

In Secure state, each bit controls whether instruction tracing is enabled for the corresponding exception level:

0The trace unit generates instruction trace, in Secure state, for exception level n.
1The trace unit generates instruction trace, in Secure state, for exception level n.

The exception levels are:

Bit[16]Exception level 0.
Bit[17]res0.
Bit[18]res0. EXLEVEL_S[2] is never implemented.
Bit[19]Exception level 3.
[15:12] - res0.
[11] TRCERR

Selects whether a system error exception must always be traced:

0System error exception is traced only if the instruction or exception immediately before the system error exception is traced.
1System error exception is always traced regardless of the value of ViewInst.
[10] TRCRESET

Selects whether a reset exception must always be traced:

0Reset exception is traced only if the instruction or exception immediately before the reset exception is traced.
1Reset exception is always traced regardless of the value of ViewInst.
[9] SSSTATUS

Indicates the current status of the start/stop logic:

0Start/stop logic is in the stopped state.
1Start/stop logic is in the started state.
[8] - res0.
[7:0] EVENT

An event selector.

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