A1.1.1 The CoreSight debug environment

The CoreSight debug environment consists of a software debugger that provides a user interface to ETM-M33. ETM-M33 is configured for instruction trace and it has a single 8-bit ATB interface.

ETM-M33 is designed for use with CoreSight, an extensible system-wide debug and trace architecture from ARM. See the ARM® CoreSight™ SoC-400 User Guide for more information about how to test the integration of ETM-M33 in a full CoreSight system.

A software debugger provides a user interface to ETM-M33. You can use this interface to:

  • Configure ETM-M33 facilities such as filtering.
  • Configure optional trace features such as cycle counting.
  • Configure the other CoreSight components such as the Trace Port Interface Unit (TPIU).
  • Access the processor debug and performance monitor units.

ETM-M33 outputs its trace to the AMBA 4 Advanced Trace Bus (ATB) interface.

You can use the CoreSight infrastructure to design systems that provide the following options:

  • Export the trace information through a trace port. An external Trace Port Analyzer (TPA) captures the trace information as the figure in this section shows.
  • Write the trace information to a trace-capable device that can access local or system memory. You can read out the trace at low speed using a JTAG or Serial Wire interface.

The debugger has a copy of the executed image from memory and the captured trace information from the TPA or on-chip trace buffer. It decompresses the image to provide full disassembly, with symbols, of the code that was executed. ETM-M33 generates trace information that gives the debugger the capability to link this data back to the original high-level source code. This provides a visualization of how the code was executed on the Cortex®‑M33 processor.

The following figure shows an example of how ETM-M33 fits into a CoreSight debug environment to provide instruction trace capabilities in a single processor system. In this example, the external debug software configures the trace and debug components through the Debug Access Port (DAP). The top-level ROM table contains a unique identification code for the SoC and the base addresses of the components that are connected to the External PPB on the Cortex‑M33 processor. The ETM-M33 trace interfaces are replicated to provide on-chip storage using the CoreSight ETB or output off-chip using the TPIU. Cross-triggering operates through the Cross Trigger Interface (CTI) and Cross Trigger Matrix (CTM) components.

Figure A1-1 Example CoreSight system with ETM-M33
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The arrows on the thick lines show the transaction direction on buses, from master to slave port. Each bus contains individual signals that go from master to slave and other signals that go from slave to master.

As an alternative to using an external computer to run a software debugger, the Cortex‑M33 processor (or another processor on the SoC) can access ETM-M33 and an on-chip trace buffer to provide self-hosted debug and trace functionality.

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