A1.3 Features

This section describes the ETM-M33 features that are implementation defined based on either the number of times the feature is implemented, or the size of the feature.

See the ARM® Embedded Trace Macrocell Architecture Specification ETMv4 for information about:

  • The trace protocol.
  • The features of ETMv4.2.
  • Controlling tracing using triggering and filtering resources.

The following table shows the ETM-M33 features that are implementation defined, in terms of either:

  • The number of times the feature is implemented.
  • The size of the feature.

Table A1-1 ETM-M33 features with implementation-defined number of instances or size

Feature

ETM-M33 configuration

Notes
Address comparators 0 pairs See bits[3:0] of the B1.21 ID Register 4.
Data value comparators 0 See bits[7:4] of the B1.21 ID Register 4.
Context ID comparators 0 See bits[27:24] B1.21 ID Register 4.
Single-Shot comparator resource 1 The single-shot comparators are only sensitive to the processor comparator inputs.
Counters 1a See bits[30:28] of the B1.20 ID Register 3.
Cycle count size 12 bits See bits[28:25] of the B1.19 ID Register 2.
Sequencer 0 See bits[27:25] of the B1.22 ID Register 5.
Processor comparator inputs 4 See bits[15:12] of the B1.22 ID Register 5.
External inputs 4 See bits[8:0] of the B1.22 ID Register 5.
External outputs 2 -
External input selectors 0 See bits[11:9] of the B1.22 ID Register 5.
Resource selector pairs 2 See bits[19:16] of the B1.21 ID Register 4.
Instruction trace port size 8-bit -
Instruction FIFO 64 byte with 8-bit output Uses ATB
Claim tag bits 4 -

The following table shows the optional features of the ETM architecture that ETM-M33 implements.

Table A1-2 ETM-M33 implementation of optional features

Feature Implemented Notes
Configurable FIFO No -
Trace Start/Stop block Yes -
Trace all branches option Yes See bit[5] of the B1.17 ID Register 0.
Trace of conditional instructions Yes See bits[13:12] and bit[6] of the B1.17 ID Register 0.
Cycle counting in instruction trace Yes See bit[7] of the B1.17 ID Register 0.
Data address comparison No The Cortex®‑M33 processor does not implement data address comparison.
OS Lock mechanism No The Cortex‑M33 processor does not implement OS Lock.
Secure non-invasive debug Yes The Cortex‑M33 processor implements optional Security Extensions.
Context ID tracing No See bits[9:5] of the B1.19 ID Register 2.
Trace output Yes ATB
Timestamp size 64-bit See bits[28:24] of the B1.17 ID Register 0.
Memory mapped access to ETM-M33 registers Yes See the ARM® Embedded Trace Macrocell Architecture Specification ETMv4 for more information about the Access permissions behaviors on register accesses for different trace unit states.

External debugger access to ETM-M33 registers

Yes
System instruction access to ETM-M33 registers No
VMID comparator support No See bits[31:28] of the B1.21 ID Register 4.
ATB trigger support Yes See bit[22] of the B1.22 ID Register 5.
a

Reduced function counter implementation.

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