B1.28 Power Down Status Register

The TRCPDSR indicates the power down status of the ETM-M33.

Usage constraints
There are no usage constraints.
Available in all configurations.
See the register summary in Table B1-1 ETM-M33 register summary and Table B1-8 Power control registers.

The following figure shows the TRCPDSR bit assignments.

Figure B1-31 TRCPDSR bit assignments
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The following table shows the TRCPDSR bit assignments.

Table B1-41 TRCPDSR bit assignments

Bits Name Function
[31:6] - res0.
[5] OSLK res0.
[4:2] - res0.
[1] STICKYPD Sticky power down state.
0Trace register power has not been removed since the TRCPDSR was last read.
1Trace register power has been removed since the TRCPDSR was last read.

This bit is set to 1 when power to the ETM-M33 registers is removed, to indicate that programming state has been lost. It is cleared after a read of the TRCPDSR.

[0] POWER Indicates ETM-M33 is powered up:
1ETM-M33 is powered up. All registers are accessible.

If a system implementation allows ETM-M33 to be powered down independently of the debug power domain, the system must ensure:

  • Accesses to ETM-M33 complete correctly.
  • Reads to this location return 0 to indicate that ETM-M33 is powered down.
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