Arm® Cortex®‑M33 Devices Generic User Guide

Revision r0p4


Table of Contents

Preface
About this book
Product revision status
Intended audience
Using this book
Additional reading
Feedback
Feedback on this product
Feedback on content
1 Introduction
1.1 About the Cortex®‑M33 processor and core peripherals
1.1.1 System-level interface
1.1.2 Security Extension
1.1.3 Integrated configurable debug
1.1.4 Processor features and benefits summary
1.1.5 Processor core peripherals
1.2 Arm®v8‑M enablement
2 The Cortex®‑M33 Processor
2.1 Programmer's model
2.1.1 Processor modes and privilege levels for software execution
2.1.2 Security states
2.1.3 Core registers
2.1.4 Exceptions and interrupts
2.1.5 Data types and data memory accesses
2.1.6 The Cortex Microcontroller Software Interface Standard
2.2 Memory model
2.2.1 Processor memory map
2.2.2 Memory regions, types, and attributes
2.2.3 Device memory
2.2.4 Secure memory system and memory partitioning
2.2.5 Behavior of memory accesses
2.2.6 Software ordering of memory accesses
2.2.7 Memory endianness
2.2.8 Synchronization primitives
2.2.9 Programming hints for the synchronization primitives
2.3 Exception model
2.3.1 Exception states
2.3.2 Exception types
2.3.3 Exception handlers
2.3.4 Vector table
2.3.5 Exception priorities
2.3.6 Interrupt priority grouping
2.3.7 Exception entry and return
2.4 Security state switches
2.5 Fault handling
2.5.1 Fault types reference table
2.5.2 Fault escalation to HardFault
2.5.3 Fault status registers and fault address registers
2.5.4 Lockup
2.6 Power management
2.6.1 Entering sleep mode
2.6.2 Wakeup from sleep mode
2.6.3 The Wakeup Interrupt Controller
2.6.4 The external event input
2.6.5 Power management programming hints
3 The Cortex®‑M33 Instruction Set
3.1 Cortex®‑M33 instructions
3.1.1 Binary compatibility with other Cortex processors
3.2 CMSIS functions
3.2.1 List of CMSIS functions to generate some processor instructions
3.2.2 CMSE
3.2.3 CMSIS functions to access the special registers
3.2.4 CMSIS functions to access the Non-secure special registers
3.3 About the instruction descriptions
3.3.1 Operands
3.3.2 Restrictions when using PC or SP
3.3.3 Flexible second operand
3.3.4 Shift Operations
3.3.5 Address alignment
3.3.6 PC‑relative expressions
3.3.7 Conditional execution
3.3.8 Instruction width selection
3.4 General data processing instructions
3.4.1 List of data processing instructions
3.4.2 ADD, ADC, SUB, SBC, and RSB
3.4.3 AND, ORR, EOR, BIC, and ORN
3.4.4 ASR, LSL, LSR, ROR, and RRX
3.4.5 CLZ
3.4.6 CMP and CMN
3.4.7 MOV and MVN
3.4.8 MOVT
3.4.9 REV, REV16, REVSH, and RBIT
3.4.10 SADD16 and SADD8
3.4.11 SASX and SSAX
3.4.12 SEL
3.4.13 SHADD16 and SHADD8
3.4.14 SHASX and SHSAX
3.4.15 SHSUB16 and SHSUB8
3.4.16 SSUB16 and SSUB8
3.4.17 TST and TEQ
3.4.18 UADD16 and UADD8
3.4.19 UASX and USAX
3.4.20 UHADD16 and UHADD8
3.4.21 UHASX and UHSAX
3.4.22 UHSUB16 and UHSUB8
3.4.23 USAD8
3.4.24 USADA8
3.4.25 USUB16 and USUB8
3.5 Coprocessor instructions
3.5.1 List of coprocessor instructions
3.5.2 Coprocessor intrinsics
3.5.3 CDP and CDP2
3.5.4 MCR and MCR2
3.5.5 MCRR and MCRR2
3.5.6 MRC and MRC2
3.5.7 MRRC and MRRC2
3.6 Multiply and divide instructions
3.6.1 List of multiply and divide instructions
3.6.2 MUL, MLA, and MLS
3.6.3 SDIV and UDIV
3.6.4 SMLAWB, SMLAWT, SMLABB, SMLABT, SMLATB, and SMLATT
3.6.5 SMLAD and SMLADX
3.6.6 SMLALD, SMLALDX, SMLALBB, SMLALBT, SMLALTB, and SMLALTT
3.6.7 SMLSD and SMLSLD
3.6.8 SMMLA and SMMLS
3.6.9 SMMUL
3.6.10 SMUAD and SMUSD
3.6.11 SMUL and SMULW
3.6.12 UMULL, UMAAL, UMLAL, SMULL, and SMLAL
3.7 Saturating instructions
3.7.1 List of saturating instructions
3.7.2 SSAT and USAT
3.7.3 SSAT16 and USAT16
3.7.4 QADD and QSUB
3.7.5 QASX and QSAX
3.7.6 QDADD and QDSUB
3.7.7 UQASX and UQSAX
3.7.8 UQADD and UQSUB
3.8 Packing and unpacking instructions
3.8.1 List of packing and unpacking instructions
3.8.2 PKHBT and PKHTB
3.8.3 SXTA and UXTA
3.8.4 SXT and UXT
3.9 Bit field instructions
3.9.1 List of bit field instructions
3.9.2 BFC and BFI
3.9.3 SBFX and UBFX
3.10 Branch and control instructions
3.10.1 List of branch and control instructions
3.10.2 B, BL, BX, and BLX
3.10.3 BXNS and BLXNS
3.10.4 CBZ and CBNZ
3.10.5 IT
3.10.6 TBB and TBH
3.11 Floating-point instructions
3.11.1 List of floating-point instructions
3.11.2 FLDMDBX, FLDMIAX
3.11.3 FSTMDBX, FSTMIAX
3.11.4 VABS
3.11.5 VADD
3.11.6 VCMP and VCMPE
3.11.7 VCVT and VCVTR between floating-point and integer
3.11.8 VCVT between floating-point and fixed-point
3.11.9 VDIV
3.11.10 VFMA and VFMS
3.11.11 VFNMA and VFNMS
3.11.12 VLDM
3.11.13 VLDR
3.11.14 VLLDM
3.11.15 VLSTM
3.11.16 VMLA and VMLS
3.11.17 VMOV Immediate
3.11.18 VMOV Register
3.11.19 VMOV scalar to core register
3.11.20 VMOV core register to single-precision
3.11.21 VMOV two core registers to two single-precision registers
3.11.22 VMOV two core registers and a double-precision register
3.11.23 VMOV core register to scalar
3.11.24 VMRS
3.11.25 VMSR
3.11.26 VMUL
3.11.27 VNEG
3.11.28 VNMLA, VNMLS and VNMUL
3.11.29 VPOP
3.11.30 VPUSH
3.11.31 VSQRT
3.11.32 VSTM
3.11.33 VSTR
3.11.34 VSUB
3.11.35 VSEL
3.11.36 VCVTA, VCVTM VCVTN, and VCVTP
3.11.37 VCVTB and VCVTT
3.11.38 VMAXNM and VMINNM
3.11.39 VRINTR and VRINTX
3.11.40 VRINTA, VRINTN, VRINTP, VRINTM, and VRINTZ
3.12 Miscellaneous instructions
3.12.1 List of miscellaneous instructions
3.12.2 BKPT
3.12.3 CPS
3.12.4 CPY
3.12.5 DMB
3.12.6 DSB
3.12.7 ISB
3.12.8 MRS
3.12.9 MSR
3.12.10 NOP
3.12.11 SEV
3.12.12 SG
3.12.13 SVC
3.12.14 TT, TTT, TTA, and TTAT
3.12.15 UDF
3.12.16 WFE
3.12.17 WFI
3.12.18 YIELD
3.13 Memory access instructions
3.13.1 List of memory access instructions
3.13.2 ADR
3.13.3 LDR and STR, immediate offset
3.13.4 LDR and STR, register offset
3.13.5 LDR and STR, unprivileged
3.13.6 LDR, PC‑relative
3.13.7 LDM and STM
3.13.8 PLD
3.13.9 PUSH and POP
3.13.10 LDA and STL
3.13.11 LDREX and STREX
3.13.12 LDAEX and STLEX
3.13.13 CLREX
4 The Cortex®‑M33 Peripherals
4.1 About the Cortex®‑M33 peripherals
4.2 System Control Block
4.2.1 System control block registers summary
4.2.2 Auxiliary Control Register
4.2.3 CPUID Base Register
4.2.4 Interrupt Control and State Register
4.2.5 Vector Table Offset Register
4.2.6 Application Interrupt and Reset Control Register
4.2.7 System Control Register
4.2.8 Configuration and Control Register
4.2.9 System Handler Priority Registers
4.2.10 System Handler Control and State Register
4.2.11 Configurable Fault Status Register
4.2.12 HardFault Status Register
4.2.13 MemManage Fault Address Register
4.2.14 BusFault Address Register
4.2.15 Coprocessor Access Control Register
4.2.16 Non-secure Access Control Register
4.2.17 System control block design hints and tips
4.3 System timer, SysTick
4.3.1 SysTick Control and Status Register
4.3.2 SysTick Reload Value Register
4.3.3 SysTick Current Value Register
4.3.4 SysTick Calibration Value Register
4.3.5 SysTick usage hints and tips
4.4 Nested Vectored Interrupt Controller
4.4.1 Accessing the NVIC registers using CMSIS
4.4.2 Interrupt Set Enable Registers
4.4.3 Interrupt Clear Enable Registers
4.4.4 Interrupt Set Pending Registers
4.4.5 Interrupt Clear Pending Registers
4.4.6 Interrupt Active Bit Registers
4.4.7 Interrupt Target Non-secure Registers
4.4.8 Interrupt Priority Registers
4.4.9 Software Trigger Interrupt Register
4.4.10 Level-sensitive and pulse interrupts
4.4.11 NVIC usage hints and tips
4.5 Security Attribution and Memory Protection
4.5.1 Security Attribution Unit
4.5.2 Security Attribution Unit Control Register
4.5.3 Security Attribution Unit Type Register
4.5.4 Security Attribution Unit Region Number Register
4.5.5 Security Attribution Unit Region Base Address Register
4.5.6 Security Attribution Unit Region Limit Address Register
4.5.7 Secure Fault Status Register
4.5.8 Secure Fault Address Register
4.5.9 Memory Protection Unit
4.5.10 MPU Type Register
4.5.11 MPU Control Register
4.5.12 MPU Region Number Register
4.5.13 MPU Region Base Address Register
4.5.14 MPU Region Base Address Register Alias, n=1-3
4.5.15 MPU Region Limit Address Register Alias, n=1-3
4.5.16 MPU Region Limit Address Register
4.5.17 MPU Memory Attribute Indirection Registers 0 and 1
4.5.18 MPU mismatch
4.5.19 Updating protected memory regions
4.5.20 MPU design hints and tips
4.6 Floating-Point Unit
4.6.1 Floating-Point Unit
4.6.2 Floating-point Context Control Register
4.6.3 Floating-point Context Address Register
4.6.4 Floating-point Status Control Register
4.6.5 Floating-point Default Status Control Register
4.6.6 Code sequence for enabling the FPU
A Cortex®‑M33 Options
A.1 Processor implementation options
B Revisions
B.1 Revisions

Release Information

Document History
Issue Date Confidentiality Change
0002-00 11 September 2017 Non-Confidential First release for r0p2
0003-00 28 November 2017 Non-Confidential First release for r0p4
0004-00 10 April 2018 Non-Confidential First release for r0p4

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