2.3 Floating-point Control Register

The FPCR characteristics are:

Purpose
Controls floating-point extension behavior.
Usage constraints

This register is accessible as follows:

EL0

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

RW RW RW RW RW RW
Configurations

The named fields in this register map to the equivalent fields in the AArch32 FPSCR. See 3.4 Floating-Point Status and Control Register.

Attributes
FPCR is a 32-bit register.
Figure 2-1 FPCR bit assignments
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[31:27]

Reserved, res0.

AHP, [26]

Alternative half-precision control bit. The possible values are:

0IEEE half-precision format selected. This is the reset value.
1Alternative half-precision format selected.
DN, [25]

Default NaN mode control bit. The possible values are:

0NaN operands propagate through to the output of a floating-point operation. This is the reset value.
1Any operation involving one or more NaNs returns the Default NaN.
FZ, [24]

Flush-to-zero mode control bit. The possible values are:

0Flush-to-zero mode disabled. Behavior of the floating-point system is fully compliant with the IEEE 754 standard. This is the reset value.
1Flush-to-zero mode enabled.
RMode, [23:22]

Rounding Mode control field. The encoding of this field is:

0b00Round to Nearest (RN) mode. This is the reset value.
0b01Round towards Plus Infinity (RP) mode.
0b10Round towards Minus Infinity (RM) mode.
0b11Round towards Zero (RZ) mode.
[21:0]
Reserved, res0.

To access the FPCR:

MRS <Xt>, FPCR ; Read FPCR into XtMSR FPCR, <Xt> ; Write Xt to FPCR

Table 2-3 FPCR access encoding

op0 op1 CRn CRm op2
11 011 0100 0100 000
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