2.7 Media and VFP Feature Register 2

The MVFR2_EL1 characteristics are:

Purpose
Describes the features provided by the AArch32 Advanced SIMD and floating-point implementation.
Usage constraints

This register is accessible as follows:

EL0 EL1(NS) EL1(S) EL2 EL3 (SCR.NS = 1) EL3(SCR.NS = 0)
- RO RO RO RO RO
Configurations

MVFR2_EL1 is architecturally mapped to AArch32 register MVFR2. See 3.7 Media and VFP Feature Register 2.

Attributes
MVFR2_EL1 is a 32-bit register.
Figure 2-5 MVFR2_EL1 bit assignments
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[31:8]

Reserved, res0.

FPMisc, [7:4]

Indicates support for miscellaneous floating-point features.

0x4

Supports:

  • Floating-point selection.
  • Floating-point Conversion to Integer with Directed Rounding modes.
  • Floating-point Round to Integral Floating-point.
  • Floating-point MaxNum and MinNum.
SIMDMisc, [3:0]

Indicates support for miscellaneous Advanced SIMD features.

0x3

Supports:

  • Floating-point Conversion to Integer with Directed Rounding modes.
  • Floating-point Round to Integral Floating-point.
  • Floating-point MaxNum and MinNum.

To access the MVFR2_EL1:

MRS <Xt>, MVFR2_EL1 ; Read MVFR2_EL1 into Xt

The following table shows the register access encoding.

Table 2-7 MVFR2_EL1 access encoding

op0 op1 CRn CRm op2
11 000 0000 0011 010
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