2.8 Floating-point Exception Control Register

The FPEXC32_EL2 characteristics are:

Purpose
Provides access to the AArch32 register FPEXC from AArch64 state only. Its value has no effect on execution in AArch64 state.
Usage constraints

This register is accessible as follows:

EL0

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - - RW RW RW
Configurations

FPEXC32_EL2 is architecturally mapped to AArch32 register FPEXC. See 3.8 Floating-Point Exception Control register.

Attributes
FPEXC32_EL2 is a 32-bit register.
Figure 2-6 FPEXC32_EL2 bit assignments
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EX, [31]

Exception bit.

res0The Cortex®‑A35 processor implementation does not generate asynchronous floating-point exceptions.
EN, [30]

Enable bit. A global enable for the Advanced SIMD and floating-point support:

0The Advanced SIMD and floating-point support is disabled. This is the reset value.
1The Advanced SIMD and floating-point support is enabled and operates normally.

This bit applies only to AArch32 execution, and only when EL1 is not AArch64.

[29:11]
Reserved, res0.
[10:8]
Reserved, res1.
[7:0]
Reserved, res0.

To access the FPEXC32_EL2:

MRS <Xt>, FPEXC32_EL2 ; Read FPEXC32_EL2 into Xt
MSR FPEXC32_EL2, <Xt> ; Write Xt to FPEXC32_EL2

See also 2.1 Accessing the AArch64 feature identification registers.

The following table shows the register access encoding.

Table 2-8 FPEXC32_EL2 access encoding

op0 op1 CRn CRm op2
11 100 0101 0011 000
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