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The FPEXC32_EL2 characteristics are:
This register is accessible as follows:
(SCR.NS = 1)
(SCR.NS = 0)
FPEXC32_EL2 is architecturally mapped to AArch32 register FPEXC. See 3.8 Floating-Point Exception Control register.
|res0||The Cortex®‑A35 processor implementation does not generate asynchronous floating-point exceptions.|
Enable bit. A global enable for the Advanced SIMD and floating-point support:
|The Advanced SIMD and floating-point support is disabled. This is the reset value.|
|The Advanced SIMD and floating-point support is enabled and operates normally.|
This bit applies only to AArch32 execution, and only when EL1 is not AArch64.
To access the FPEXC32_EL2:
MRS <Xt>, FPEXC32_EL2 ; Read FPEXC32_EL2 into Xt MSR FPEXC32_EL2, <Xt> ; Write Xt to FPEXC32_EL2
The following table shows the register access encoding.
Table 2-8 FPEXC32_EL2 access encoding