ARM® Cortex®‑A32 Processor Technical Reference Manual

Revision r0p1

Table of Contents

About this book
Product revision status
Intended audience
Using this book
Typographic conventions
Timing diagrams
Additional reading
Feedback on this product
Feedback on content
Part A Functional Description
A1 Introduction
A1.1 About the Cortex®‑A32 processor
A1.2 Features
A1.3 Implementation options
A1.4 Supported standards and specifications
A1.5 Test features
A1.6 Design tasks
A1.7 Product revisions
A2 Technical Overview
A2.1 Components
A2.2 Interfaces
A2.3 About system control
A2.4 About the Generic Timer
A2.5 About the memory model
A3 Clocks, Resets, and Input Synchronization
A3.1 Clocks
A3.2 Input synchronization
A3.3 Resets
A4 Power Management
A4.1 Power domains
A4.2 Power modes
A4.3 Core Wait for Interrupt
A4.4 Core Wait for Event
A4.5 L2 Wait for Interrupt
A4.6 Powering down an individual core
A4.7 Powering up an individual core
A4.8 Powering down the processor without system driven L2 flush
A4.9 Powering up the processor without system driven L2 flush
A4.10 Powering down the processor with system driven L2 flush
A4.11 Powering up the processor with system driven L2 flush
A4.12 Entering Dormant mode
A4.13 Exiting Dormant mode
A4.14 Event communication using WFE or SEV
A4.15 Communication to the Power Management Controller
A4.16 STANDBYWFI[3:0] and STANDBYWFIL2 signals
A4.17 Q-channel
A5 Cache Behavior and Cache Protection
A5.1 Cached memory types
A5.2 Coherency between data caches with the MOESI protocol
A5.3 Cache misses, unexpected cache hits, and speculative fetches
A5.4 Disabling a cache
A5.5 Invalidating or cleaning a cache
A5.6 About read allocate mode
A5.7 About cache protection
A5.8 Error reporting
A5.9 Error injection
A6 L1 Memory System
A6.1 About the L1 memory system
A6.2 TLB Organization
A6.3 Program flow prediction
A6.4 About the internal exclusive monitor
A6.5 About data prefetching
A7 L2 Memory System
A7.1 About the L2 memory system
A7.2 Snoop and maintenance requests
A7.3 Support for memory types
A7.4 Memory type information exported from the processor
A7.5 Handling of external aborts
A8 AXI Master Interface
A8.1 About the AXI master interface
A8.2 AXI privilege information
A8.3 AXI transactions
A8.4 Attributes of the AXI master interface
A9 ACE Master Interface
A9.1 About the ACE master interface
A9.2 ACE configurations
A9.3 ACE privilege information
A9.4 ACE transactions
A9.5 Attributes of the ACE master interface
A9.6 Snoop channel properties
A9.7 AXI compatibility mode
A10 CHI Master Interface
A10.1 About the CHI master interface
A10.2 CHI configurations
A10.3 Attributes of the CHI master interface
A10.4 CHI channel properties
A10.5 CHI transactions
A11 ACP Slave Interface
A11.1 About the ACP
A11.2 Transfer size support
A11.3 ACP performance
A11.4 ACP user signals
A12 GIC CPU Interface
A12.1 Bypassing the GIC CPU Interface
A12.2 Memory map for the GIC CPU interface
Part B Register Descriptions
B1 AArch32 system registers
B1.1 AArch32 register summary
B1.2 c0 registers
B1.3 c1 registers
B1.4 c2 registers
B1.5 c3 registers
B1.6 c4 registers
B1.7 c5 registers
B1.8 c6 registers
B1.9 c7 registers
B1.10 c7 system operations
B1.11 c8 system operations
B1.12 c9 registers
B1.13 c10 registers
B1.14 c11 registers
B1.15 c12 registers
B1.16 c13 registers
B1.17 c14 registers
B1.18 c15 registers
B1.19 64-bit registers
B1.20 AArch32 Identification registers
B1.21 AArch32 Virtual memory control registers
B1.22 AArch32 Fault handling registers
B1.23 AArch32 Other System control registers
B1.24 AArch32 Address registers
B1.25 AArch32 Thread registers
B1.26 AArch32 Performance monitor registers
B1.27 AArch32 Secure registers
B1.28 AArch32 Virtualization registers
B1.29 AArch32 GIC system registers
B1.30 AArch32 Generic Timer registers
B1.31 AArch32 Implementation defined registers
B1.32 Auxiliary Control Register
B1.33 Auxiliary Data Fault Status Register
B1.34 Auxiliary ID Register
B1.35 Auxiliary Instruction Fault Status Register
B1.36 Auxiliary Memory Attribute Indirection Register 0
B1.37 Auxiliary Memory Attribute Indirection Register 1
B1.38 Configuration Base Address Register
B1.39 Cache Size ID Register
B1.40 Cache Level ID Register
B1.41 Architectural Feature Access Control Register
B1.42 CPU Auxiliary Control Register
B1.43 CPU Extended Control Register
B1.44 CPU Memory Error Syndrome Register
B1.45 Cache Size Selection Register
B1.46 Cache Type Register
B1.47 Domain Access Control Register
B1.48 Data Fault Address Register
B1.49 Data Fault Status Register
B1.50 DFSR with Short-descriptor translation table format
B1.51 DFSR with Long-descriptor translation table format
B1.52 Encoding of ISS[24:20] when HSR[31:30] is 0b00
B1.53 FCSE Process ID Register
B1.54 Hyp Auxiliary Configuration Register
B1.55 Hyp Auxiliary Control Register
B1.56 Hyp Auxiliary Data Fault Status Syndrome Register
B1.57 Hyp Auxiliary Instruction Fault Status Syndrome Register
B1.58 Hyp Auxiliary Memory Attribute Indirection Register 0
B1.59 Hyp Auxiliary Memory Attribute Indirection Register 1
B1.60 Hyp Architectural Feature Trap Register
B1.61 Hyp Configuration Register
B1.62 Hyp Configuration Register 2
B1.63 Hyp Debug Control Register
B1.64 Hyp Data Fault Address Register
B1.65 Hyp Instruction Fault Address Register
B1.66 Hyp IPA Fault Address Register
B1.67 Hyp System Control Register
B1.68 Hyp Syndrome Register
B1.69 Hyp System Trap Register
B1.70 Hyp Translation Control Register
B1.71 Hyp Vector Base Address Register
B1.72 Auxiliary Feature Register 0
B1.73 Debug Feature Register 0
B1.74 Instruction Set Attribute Register 0
B1.75 Instruction Set Attribute Register 1
B1.76 Instruction Set Attribute Register 2
B1.77 Instruction Set Attribute Register 3
B1.78 Instruction Set Attribute Register 4
B1.79 Instruction Set Attribute Register 5
B1.80 Memory Model Feature Register 0
B1.81 Memory Model Feature Register 1
B1.82 Memory Model Feature Register 2
B1.83 Memory Model Feature Register 3
B1.84 Processor Feature Register 0
B1.85 Processor Feature Register 1
B1.86 Instruction Fault Address Register
B1.87 Instruction Fault Status Register
B1.88 IFSR with Short-descriptor translation table format
B1.89 IFSR with Long-descriptor translation table format
B1.90 Interrupt Status Register
B1.91 L2 Auxiliary Control Register
B1.92 L2 Control Register
B1.93 L2 Extended Control Register
B1.94 L2 Memory Error Syndrome Register
B1.95 Memory Attribute Indirection Registers 0 and 1
B1.96 Main ID Register
B1.97 Multiprocessor Affinity Register
B1.98 Non-Secure Access Control Register
B1.99 Normal Memory Remap Register
B1.100 Physical Address Register
B1.101 Primary Region Remap Register
B1.102 Revision ID Register
B1.103 Reset Management Register
B1.104 Secure Configuration Register
B1.105 System Control Register
B1.106 Secure Debug Control Register
B1.107 Secure Debug Enable Register
B1.108 TCM Type Register
B1.109 TLB Type Register
B1.110 Translation Table Base Control Register
B1.111 TTBCR with Short-descriptor translation table format
B1.112 TTBCR with Long-descriptor translation table format
B1.113 Translation Table Base Register 0
B1.114 TTBR0 with Short-descriptor translation table format
B1.115 TTBR0 with Long-descriptor translation table format
B1.116 Translation Table Base Register 1
B1.117 TTBR1 with Short-descriptor translation table format
B1.118 TTBR1 with Long-descriptor translation table format
B1.119 Vector Base Address Register
B1.120 Virtualization Multiprocessor ID Register
B1.121 Virtualization Processor ID Register
B1.122 Virtualization Translation Control Register
B2 GIC registers
B2.1 CPU interface register summary
B2.2 Active Priority Register
B2.3 CPU Interface Identification Register
B2.4 Virtual interface control register summary
B2.5 VGIC Type Register
B2.6 Virtual CPU interface register summary
B2.7 VM Active Priority Register
B2.8 VM CPU Interface Identification Register
B3 Generic Timer registers
B3.1 AArch32 Generic Timer register summary
Part C Debug
C1 Debug
C1.1 About debug methods
C1.2 Debug access
C1.3 Effects of resets on debug registers
C1.4 External access permissions to debug registers
C1.5 Debug events
C1.6 Debug memory map
C1.7 Debug signals
C1.8 Changing the authentication signals for debug
C2.1 About the PMU
C2.2 External register access permissions to the PMU registers
C2.3 Performance monitoring events
C2.4 PMU interrupts
C2.5 Exporting PMU events
C3.1 About the ETM
C3.2 Configuration options for the ETM unit and trace resources
C3.3 Resetting the ETM
C3.4 Programming and reading ETM trace unit registers
C4.1 About the cross-trigger
C4.2 Cross-trigger inputs and outputs
C5 Direct access to internal memory
C5.1 About direct access to internal memory
C5.2 Encoding for tag and data in the L1 instruction cache
C5.3 Encoding for tag and data in the L1 data cache
C5.4 Encoding for the main TLB RAM
C5.5 Encoding for walk cache
C5.6 Encoding for IPA cache
C6 AArch32 debug registers
C6.1 AArch32 debug register summary
C6.2 Debug Breakpoint Control Registers
C6.3 Debug Watchpoint Control Registers
C6.4 Debug ID Register
C6.5 Debug Device ID Register
C6.6 Debug Device ID Register 1
C7 Memory-mapped debug registers
C7.1 Memory-mapped debug register summary
C7.2 External Debug Reserve Control Register
C7.3 External Debug Integration Mode Control Register
C7.4 External Debug Device ID Register 0
C7.5 External Debug Device ID Register 1
C7.6 External Debug Processor Feature Register
C7.7 External Debug Feature Register
C7.8 External Debug AArch32 Processor Feature Register
C7.9 External Debug Peripheral Identification Registers
C7.10 External Debug Peripheral Identification Register 0
C7.11 External Debug Peripheral Identification Register 1
C7.12 External Debug Peripheral Identification Register 2
C7.13 External Debug Peripheral Identification Register 3
C7.14 External Debug Peripheral Identification Register 4
C7.15 External Debug Peripheral Identification Register 5-7
C7.16 External Debug Component Identification Registers
C7.17 External Debug Component Identification Register 0
C7.18 External Debug Component Identification Register 1
C7.19 External Debug Component Identification Register 2
C7.20 External Debug Component Identification Register 3
C8 ROM table
C8.1 About the ROM table
C8.2 ROM table register interface
C8.3 ROM table register summary
C8.4 ROM entry registers
C8.5 ROM Table Peripheral Identification Registers
C8.6 ROM Table Peripheral Identification Register 0
C8.7 ROM Table Peripheral Identification Register 1
C8.8 ROM Table Peripheral Identification Register 2
C8.9 ROM Table Peripheral Identification Register 3
C8.10 ROM Table Peripheral Identification Register 4
C8.11 ROM Table Peripheral Identification Register 5-7
C8.12 ROM Table Component Identification Registers
C8.13 ROM Table Component Identification Register 0
C8.14 ROM Table Component Identification Register 1
C8.15 ROM Table Component Identification Register 2
C8.16 ROM Table Component Identification Register 3
C9 PMU registers
C9.1 AArch32 PMU register summary
C9.2 Performance Monitors Control Register
C9.3 Performance Monitors Common Event Identification Register 0
C9.4 Performance Monitors Common Event Identification Register 1
C9.5 Memory-mapped PMU register summary
C9.6 Performance Monitors Configuration Register
C9.7 Performance Monitors Peripheral Identification Registers
C9.8 Performance Monitors Peripheral Identification Register 0
C9.9 Performance Monitors Peripheral Identification Register 1
C9.10 Performance Monitors Peripheral Identification Register 2
C9.11 Performance Monitors Peripheral Identification Register 3
C9.12 Performance Monitors Peripheral Identification Register 4
C9.13 Performance Monitors Peripheral Identification Register 5-7
C9.14 Performance Monitors Component Identification Registers
C9.15 Performance Monitors Component Identification Register 0
C9.16 Performance Monitors Component Identification Register 1
C9.17 Performance Monitors Component Identification Register 2
C9.18 Performance Monitors Component Identification Register 3
C10 ETM registers
C10.1 ETM register summary
C10.2 Programming Control Register
C10.3 Status Register
C10.4 Trace Configuration Register
C10.5 Branch Broadcast Control Register
C10.6 Auxiliary Control Register
C10.7 Event Control 0 Register
C10.8 Event Control 1 Register
C10.9 Stall Control Register
C10.10 Global Timestamp Control Register
C10.11 Synchronization Period Register
C10.12 Cycle Count Control Register
C10.13 Trace ID Register
C10.14 ViewInst Main Control Register
C10.15 ViewInst Include-Exclude Control Register
C10.16 ViewInst Start-Stop Control Register
C10.17 Sequencer State Transition Control Registers 0-2
C10.18 Sequencer Reset Control Register
C10.19 Sequencer State Register
C10.20 External Input Select Register
C10.21 Counter Reload Value Registers 0-1
C10.22 Counter Control Register 0
C10.23 Counter Control Register 1
C10.24 Counter Value Registers 0-1
C10.25 ID Register 8
C10.26 ID Register 9
C10.27 ID Register 10
C10.28 ID Register 11
C10.29 ID Register 12
C10.30 ID Register 13
C10.31 Implementation Specific Register 0
C10.32 ID Register 0
C10.33 ID Register 1
C10.34 ID Register 2
C10.35 ID Register 3
C10.36 ID Register 4
C10.37 ID Register 5
C10.38 Resource Selection Control Registers 2-16
C10.39 Single-Shot Comparator Control Register 0
C10.40 Single-Shot Comparator Status Register 0
C10.41 OS Lock Access Register
C10.42 OS Lock Status Register
C10.43 Power Down Control Register
C10.44 Power Down Status Register
C10.45 Address Comparator Value Registers 0-7
C10.46 Address Comparator Access Type Registers 0-7
C10.47 Context ID Comparator Value Register 0
C10.48 VMID Comparator Value Register 0
C10.49 Context ID Comparator Control Register 0
C10.50 Integration ATB Identification Register
C10.51 Integration Instruction ATB Data Register
C10.52 Integration Instruction ATB In Register
C10.53 Integration Instruction ATB Out Register
C10.54 Integration Mode Control Register
C10.55 Claim Tag Set Register
C10.56 Claim Tag Clear Register
C10.57 Device Affinity Register 0
C10.58 Device Affinity Register 1
C10.59 Software Lock Access Register
C10.60 Software Lock Status Register
C10.61 Authentication Status Register
C10.62 Device Architecture Register
C10.63 Device ID Register
C10.64 Device Type Register
C10.65 ETM Peripheral Identification Registers
C10.66 ETM Peripheral Identification Register 0
C10.67 ETM Peripheral Identification Register 1
C10.68 ETM Peripheral Identification Register 2
C10.69 ETM Peripheral Identification Register 3
C10.70 ETM Peripheral Identification Register 4
C10.71 ETM Peripheral Identification Register 5-7
C10.72 ETM Component Identification Registers
C10.73 ETM Component Identification Register 0
C10.74 ETM Component Identification Register 1
C10.75 ETM Component Identification Register 2
C10.76 ETM Component Identification Register 3
C11 CTI registers
C11.1 Cross trigger register summary
C11.2 External register access permissions to the CTI registers
C11.3 CTI Device Identification Register
C11.4 CTI Integration Mode Control Register
C11.5 CTI Peripheral Identification Registers
C11.6 CTI Peripheral Identification Register 0
C11.7 CTI Peripheral Identification Register 1
C11.8 CTI Peripheral Identification Register 2
C11.9 CTI Peripheral Identification Register 3
C11.10 CTI Peripheral Identification Register 4
C11.11 CTI Peripheral Identification Register 5-7
C11.12 CTI Component Identification Registers
C11.13 CTI Component Identification Register 0
C11.14 CTI Component Identification Register 1
C11.15 CTI Component Identification Register 2
C11.16 CTI Component Identification Register 3
Part D Appendices
A Signal Descriptions
A.1 About the signal descriptions
A.2 Processor configuration signals
A.3 Clock signals
A.4 Reset signals
A.5 GIC signals
A.6 Generic Timer signals
A.7 Power management signals
A.8 L2 error signals
A.9 ACP interface signals
A.10 Broadcast signals for the memory interface
A.11 AXI interface signals
A.12 ACE interface signals
A.13 CHI interface signals
A.14 Debug signals
A.15 APB interface signals
A.16 ATB interface signals
A.17 ETM signals
A.18 PMU interface signals
A.19 CTI interface signals
A.20 DFT interface signals
A.21 MBIST interface signals
B.1 Use of R15 by Instruction
B.2 UNPREDICTABLE instructions within an IT Block
B.3 Load/Store accesses crossing page boundaries
B.4 ARMv8 Debug UNPREDICTABLE behaviors
B.5 Other UNPREDICTABLE behaviors
C Revisions
C.1 Revisions

Release Information

Document History
Issue Date Confidentiality Change
0000-00 18 March 2016 Confidential First release for r0p0
0001-00 03 February 2017 Non-Confidential First release for r0p1

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