C7.6 External Debug Processor Feature Register

The EDPFR characteristics are:

Purpose
Provides additional information about implemented PE features in AArch64.
Usage constraints

This register is accessible as follows:

Default

RO
Configurations

The EDPFR is in the Debug power domain.

Attributes
EDPFR is a 64-bit register.
Figure C7-5 EDPFR bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


[63:28]

Reserved, res0.

GIC, [27:24]

System register GIC interface. Defined values are:

0x0No System register interface to the GIC is supported.
0x1

System register interface to the GIC CPU interface is supported.

All other values are reserved.

AdvSIMD, [23:20]

Advanced SIMD. Defined values are:

0x0Advanced SIMD is implemented.
0xFAdvanced SIMD is not implemented.

All other values are reserved.

FP, [19:16]

Floating-point. Defined values are:

0x0Floating-point is implemented.
0xFFloating-point is not implemented.

All other values are reserved.

EL3 handling, [15:12]

EL3 exception handling:

0x0Instructions can be executed at EL3 in AArch32 state.
EL2 handling, [11:8]

EL2 exception handling:

0x0Instructions can be executed at EL2 in AArch32 state.
EL1 handling, [7:4]

EL1 exception handling. The possible values are:

0x0Instructions can be executed at EL1 in AArch32 state.
EL0 handling, [3:0]

EL0 exception handling. The possible values are:

0x0Instructions can be executed at EL0 in AArch32 state.

The EDPFR[31:0] can be accessed through the external debug interface, offset 0xD20.

The EDPFR[63:32] can be accessed through the external debug interface, offset 0xD24.

Non-ConfidentialPDF file icon PDF versionARM 100241_0001_00_en
Copyright © 2016, 2017 ARM Limited or its affiliates. All rights reserved.